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path: root/drivers/clk/mediatek
AgeCommit message (Expand)AuthorFilesLines
2015-07-28Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd4-2/+6
2015-07-28clk: mediatek: Add MT8173 MMPLL change rate supportJames Liao3-6/+42
2015-07-28clk: mediatek: Fix calculation of PLL rate settingsJames Liao1-2/+2
2015-07-28clk: mediatek: Fix PLL registers setting flowJames Liao1-9/+12
2015-07-20clk: mediatek: Properly include clk.hStephen Boyd4-2/+6
2015-07-07clk: mediatek: mt8173: Fix enabling of critical clocksSascha Hauer1-5/+21
2015-06-05clk: mediatek: Fix apmixedsys clock registrationJames Liao2-2/+2
2015-05-20clk: mediatek: Initialize clk_init_dataRicky Liang2-2/+2
2015-05-06clk: mediatek: Add basic clocks for Mediatek MT8173.James Liao2-0/+831
2015-05-06clk: mediatek: Add basic clocks for Mediatek MT8135.James Liao2-0/+645
2015-05-06clk: mediatek: Add reset controller supportSascha Hauer3-0/+108
2015-05-06clk: mediatek: Add initial common clock support for Mediatek SoCs.James Liao6-0/+898