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path: root/drivers/clk/mediatek
AgeCommit message (Expand)AuthorFilesLines
2021-11-03clk:mediatek: remove duplicate include in clk-mt8195-imp_iic_wrap.cRan Jianping1-2/+0
2021-09-15clk: mediatek: Export clk_ops structures to modulesStephen Boyd1-0/+2
2021-09-15clk: mediatek: support COMMON_CLK_MT6779 module buildMiles Chen10-17/+35
2021-09-15clk: mediatek: support COMMON_CLK_MEDIATEK module buildMiles Chen8-1/+33
2021-09-15clk: mediatek: Add MT8195 apusys clock supportChun-Jie Chen2-1/+94
2021-09-15clk: mediatek: Add MT8195 imp i2c wrapper clock supportChun-Jie Chen2-1/+69
2021-09-15clk: mediatek: Add MT8195 wpesys clock supportChun-Jie Chen2-1/+145
2021-09-15clk: mediatek: Add MT8195 vppsys1 clock supportChun-Jie Chen2-1/+109
2021-09-15clk: mediatek: Add MT8195 vppsys0 clock supportChun-Jie Chen2-1/+111
2021-09-15clk: mediatek: Add MT8195 vencsys clock supportChun-Jie Chen2-1/+71
2021-09-15clk: mediatek: Add MT8195 vdosys1 clock supportChun-Jie Chen2-1/+141
2021-09-15clk: mediatek: Add MT8195 vdosys0 clock supportChun-Jie Chen2-1/+124
2021-09-15clk: mediatek: Add MT8195 vdecsys clock supportChun-Jie Chen2-1/+106
2021-09-15clk: mediatek: Add MT8195 scp adsp clock supportChun-Jie Chen2-1/+48
2021-09-15clk: mediatek: Add MT8195 mfgcfg clock supportChun-Jie Chen2-1/+48
2021-09-15clk: mediatek: Add MT8195 ipesys clock supportChun-Jie Chen2-1/+53
2021-09-15clk: mediatek: Add MT8195 imgsys clock supportChun-Jie Chen2-1/+97
2021-09-15clk: mediatek: Add MT8195 ccusys clock supportChun-Jie Chen2-1/+51
2021-09-15clk: mediatek: Add MT8195 camsys clock supportChun-Jie Chen2-1/+144
2021-09-15clk: mediatek: Add MT8195 infrastructure clock supportChun-Jie Chen2-1/+207
2021-09-15clk: mediatek: Add MT8195 peripheral clock supportChun-Jie Chen2-1/+64
2021-09-15clk: mediatek: Add MT8195 topckgen clock supportChun-Jie Chen2-1/+1274
2021-09-15clk: mediatek: Add MT8195 apmixedsys clock supportChun-Jie Chen3-0/+154
2021-09-15clk: mediatek: Fix resource leak in mtk_clk_simple_probeChun-Jie Chen1-2/+10
2021-09-15clk: mediatek: Add API for clock resource recycleChun-Jie Chen2-0/+10
2021-09-15clk: mediatek: Fix corner case of tuner_en_regChun-Jie Chen1-1/+1
2021-07-27clk: mediatek: make COMMON_CLK_MT8167* depend on COMMON_CLK_MT8167Miles Chen1-15/+10
2021-07-27clk: mediatek: Add MT8192 vencsys clock supportChun-Jie Chen3-0/+60
2021-07-27clk: mediatek: Add MT8192 vdecsys clock supportChun-Jie Chen3-0/+101
2021-07-27clk: mediatek: Add MT8192 scp adsp clock supportChun-Jie Chen3-0/+57
2021-07-27clk: mediatek: Add MT8192 msdc clock supportChun-Jie Chen3-0/+92
2021-07-27clk: mediatek: Add MT8192 mmsys clock supportChun-Jie Chen3-0/+115
2021-07-27clk: mediatek: Add MT8192 mfgcfg clock supportChun-Jie Chen3-0/+57
2021-07-27clk: mediatek: Add MT8192 mdpsys clock supportChun-Jie Chen3-0/+89
2021-07-27clk: mediatek: Add MT8192 ipesys clock supportChun-Jie Chen3-0/+64
2021-07-27clk: mediatek: Add MT8192 imp i2c wrapper clock supportChun-Jie Chen3-0/+126
2021-07-27clk: mediatek: Add MT8192 imgsys clock supportChun-Jie Chen3-0/+77
2021-07-27clk: mediatek: Add MT8192 camsys clock supportChun-Jie Chen3-0/+114
2021-07-27clk: mediatek: Add MT8192 audio clock supportChun-Jie Chen3-0/+125
2021-07-27clk: mediatek: Add MT8192 basic clocks supportChun-Jie Chen5-4/+1358
2021-07-27clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providersChun-Jie Chen2-0/+31
2021-07-27clk: mediatek: Add configurable enable control to mtk_pll_dataChun-Jie Chen2-14/+21
2021-07-27clk: mediatek: Fix asymmetrical PLL enable and disable controlChun-Jie Chen1-4/+16
2021-07-27clk: mediatek: Get regmap without syscon compatible checkChun-Jie Chen4-4/+4
2021-02-09clk: mediatek: mux: Update parent at enable timeLaurent Pinchart2-3/+30
2021-02-09clk: mediatek: mux: Drop unused clock opsLaurent Pinchart2-70/+4
2021-02-09clk: mediatek: Select all the MT8183 clocks by defaultEnric Balletbo i Serra1-0/+11
2020-12-17clk: mediatek: Make mtk_clk_register_mux() a static functionWeiyi Lu2-5/+1
2020-10-20Merge branches 'clk-simplify', 'clk-ti', 'clk-tegra', 'clk-rockchip' and 'clk...Stephen Boyd12-14/+1511
2020-10-14clk: mediatek: Add MT8167 clock supportFabien Parent8-0/+1505