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path: root/drivers/clk/meson
AgeCommit message (Expand)AuthorFilesLines
2018-07-09clk: meson: add gen_clkJerome Brunet4-3/+135
2018-07-09clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definitionJerome Brunet1-1/+0
2018-07-09clk: meson-axg: add clocks required by pcie driverYixun Lan2-1/+150
2018-07-09clk: meson: remove unused clk-audio-divider driverJerome Brunet3-119/+1
2018-07-09clk: meson: stop rate propagation for audio clocksJerome Brunet1-9/+7
2018-07-09clk: meson: axg: add the audio clock controller driverJerome Brunet4-0/+982
2018-07-09clk: meson: add axg audio sclk divider driverJerome Brunet3-1/+252
2018-07-09clk: meson: add triple phase clock driverJerome Brunet4-0/+94
2018-07-09clk: meson: add clk-phase clock driverJerome Brunet3-0/+72
2018-07-09clk: meson: clean-up meson clock configurationJerome Brunet1-9/+5
2018-07-09clk: meson: remove obsolete register accessJerome Brunet2-69/+4
2018-06-21clk: meson: audio-divider is one basedJerome Brunet1-1/+1
2018-06-19clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICALNeil Armstrong1-0/+1
2018-06-09Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds20-309/+586
2018-05-21clk: meson: axg: let mpll clocks round closestJerome Brunet1-0/+4
2018-05-21clk: meson: mpll: add round closest supportJerome Brunet2-5/+22
2018-05-21clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICALMartin Blumenstingl1-0/+7
2018-05-18clk: meson: use SPDX license identifiers consistentlyJerome Brunet13-238/+20
2018-05-15clk: meson: drop CLK_SET_RATE_PARENT flagYixun Lan1-1/+1
2018-05-15clk: meson-axg: Add AO Clock and Reset controller driverQiufang Dai4-1/+195
2018-05-15clk: meson: aoclk: refactor common code into dedicated fileYixun Lan6-62/+160
2018-05-15clk: meson: migrate to devm_of_clk_add_hw_provider APIYixun Lan1-1/+1
2018-05-15clk: meson: gxbb: add the video decoder clocksMaxime Jourdan2-1/+119
2018-05-15clk: meson: meson8b: add support for the NAND clocksMartin Blumenstingl2-1/+58
2018-05-02Merge tag 'meson-clk-fixes-4.17-1' of https://github.com/BayLibre/clk-meson i...Stephen Boyd2-4/+3
2018-04-25clk: meson: meson8b: fix meson8b_cpu_clk parent clock nameMartin Blumenstingl1-1/+2
2018-04-25clk: meson: meson8b: fix meson8b_fclk_div3_div clock nameMartin Blumenstingl1-1/+1
2018-04-25clk: meson: drop meson_aoclk_gate_regmap_opsYixun Lan1-2/+0
2018-04-16clk: meson: honor CLK_MUX_ROUND_CLOSEST in clk_regmapJerome Brunet1-1/+10
2018-03-15clk: meson: Drop unused local variable and add staticStephen Boyd3-11/+10
2018-03-13clk: meson: clean-up clk81 clocksJerome Brunet2-8/+4
2018-03-13clk: meson: add fdiv clock gatesJerome Brunet6-33/+278
2018-03-13clk: meson: add mpll pre-dividerJerome Brunet6-13/+65
2018-03-13clk: meson: axg: add hifi pll clockJerome Brunet2-1/+56
2018-03-13clk: meson: add ROUND_CLOSEST to the pll driverJerome Brunet2-4/+15
2018-03-13clk: meson: add gp0 frac parameter for axg and gxlJerome Brunet2-2/+12
2018-03-13clk: meson: improve pll driver results with fracJerome Brunet2-59/+91
2018-03-13clk: meson: remove special gp0 lock loopJerome Brunet4-15/+1
2018-03-13clk: meson: poke pll CNTL lastJerome Brunet2-3/+3
2018-03-13clk: meson: add fractional part of meson8b fixed_pllJerome Brunet1-0/+5
2018-03-13clk: meson: use hhi syscon if availableJerome Brunet3-24/+60
2018-03-13clk: meson: remove obsolete cpu_clkJerome Brunet3-190/+1
2018-03-13clk: meson: rework meson8b cpu clockJerome Brunet2-61/+119
2018-03-13clk: meson: split divider and gate part of mpllJerome Brunet8-118/+197
2018-03-13clk: meson: migrate plls clocks to clk_regmapJerome Brunet5-530/+535
2018-03-13clk: meson: migrate the audio divider clock to clk_regmapJerome Brunet3-68/+30
2018-03-13clk: meson: migrate mplls clocks to clk_regmapJerome Brunet5-354/+313
2018-03-13clk: meson: add regmap helpers for parmJerome Brunet1-0/+16
2018-03-13clk: meson: migrate muxes to clk_regmapJerome Brunet3-213/+184
2018-03-13clk: meson: migrate dividers to clk_regmapJerome Brunet3-159/+142