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path: root/drivers/clk/meson
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2018-01-11clk: meson-axg: fix potential NULL dereference in axg_clkc_probe()weiyongjun (A)1-0/+2
2018-01-03Merge tag 'meson-clk-for-v4.16-3' of git://github.com/BayLibre/clk-meson into...Stephen Boyd1-1/+1
2017-12-28clk: meson-axg: make local symbol axg_gp0_params_table staticweiyongjun (A)1-1/+1
2017-12-28clk: meson-axg: fix return value check in axg_clkc_probe()weiyongjun (A)1-1/+1
2017-12-24clk: meson: mpll: use 64-bit maths in params_from_rateMartin Blumenstingl1-1/+1
2017-12-14clk: meson-axg: add clock controller driversQiufang Dai4-0/+1071
2017-12-14clk: meson: make the spinlock naming more specificYixun Lan3-69/+69
2017-12-08clk: meson: gxbb: remove IGNORE_UNUSED from mmc clocksJerome Brunet1-13/+3
2017-11-27clk: meson: gxbb: fix wrong clock for SARADC/SANAYixun Lan1-2/+2
2017-10-20clk: meson: gxbb: Add VPU and VAPB clocks dataNeil Armstrong1-0/+292
2017-10-20clk: meson: gxbb: Add VPU and VAPB clockidsNeil Armstrong1-1/+5
2017-08-24Merge tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson into cl...Stephen Boyd10-251/+685
2017-08-04clk: meson: gxbb-aoclk: Add CEC 32k clockNeil Armstrong4-2/+231
2017-08-04clk: meson: gxbb-aoclk: Switch to regmap for register accessNeil Armstrong4-23/+95
2017-08-04clk: meson: gxbb: Add sd_emmc clk0 clocksJerome Brunet1-0/+177
2017-08-04clk: meson: gxbb: fix clk_mclk_i958 divider flagsJerome Brunet1-3/+4
2017-08-04clk: meson: gxbb: fix meson cts_amclk divider flagsJerome Brunet1-1/+2
2017-08-04clk: meson: meson8b: register the built-in reset controllerMartin Blumenstingl3-13/+156
2017-08-04clk: meson: gxbb: Add sd_emmc clk0 clkidsJerome Brunet1-2/+8
2017-08-04clk: meson-gxbb: expose almost every clock in the bindingsJerome Brunet1-110/+7
2017-08-04clk: meson8b: expose every clock in the bindingsJerome Brunet1-99/+4
2017-08-04clk: meson: gxbb: fix protection against undefined clksJerome Brunet1-0/+2
2017-08-04clk: meson: meson8b: fix protection against undefined clksJerome Brunet1-0/+1
2017-08-01clk: meson: mpll: fix mpll0 fractional part ignoredJerome Brunet4-0/+18
2017-06-17Merge tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson into ...Stephen Boyd4-19/+25
2017-06-16clk: meson: gxbb: add all clk81 parentsJerome Brunet1-5/+8
2017-06-16Merge branch 'next/headers' into next/driversJerome Brunet1-10/+10
2017-06-12clk: meson: meson8b: add compatibles for Meson8 and Meson8m2Martin Blumenstingl2-4/+7
2017-06-12clk: meson8b: export the ethernet gate clockMartin Blumenstingl1-1/+1
2017-06-12clk: meson8b: export the USB clocksMartin Blumenstingl1-5/+5
2017-06-12clk: meson8b: export the gate clock for the HW random number generatorMartin Blumenstingl1-1/+1
2017-06-12clk: meson8b: export the SDIO clockMartin Blumenstingl1-1/+1
2017-06-12clk: meson8b: export the SAR ADC clocksMartin Blumenstingl1-2/+2
2017-06-02clk: meson-gxbb: Add const to some parent name arraysStephen Boyd1-3/+3
2017-06-02Merge tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson into cl...Stephen Boyd3-74/+73
2017-05-29clk: meson-gxbb: Add EE 32K Clock for CECNeil Armstrong2-1/+58
2017-05-29clk: gxbb: remove CLK_IGNORE_UNUSED from clk81Jerome Brunet1-1/+1
2017-05-29clk: meson: meson8b: mark clk81 as criticalMartin Blumenstingl1-1/+1
2017-05-29clk: meson: gxbb: remove the "cpu_clk" from the GXBB and GXL driverMartin Blumenstingl2-62/+4
2017-05-29clk: meson-gxbb: un-export the CPU clockMartin Blumenstingl1-1/+1
2017-05-29clk: meson-gxbb: expose UART clocksHelmut Klein1-3/+3
2017-05-29clk: meson-gxbb: expose SPICC gateNeil Armstrong1-1/+1
2017-05-29clk: meson-gxbb: expose spdif master clockJerome Brunet1-2/+2
2017-05-29clk: meson-gxbb: expose i2s master clockJerome Brunet1-1/+1
2017-05-29clk: meson-gxbb: expose spdif clock gatesJerome Brunet1-2/+2
2017-05-16clk: meson: gxbb: fix build error without RESET_CONTROLLERTobias Regnery1-0/+1
2017-05-10Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds9-49/+1150
2017-05-09Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/...Linus Torvalds1-7/+14
2017-04-07clk: meson: mpll: use 64bit math in rate_from_paramsMartin Blumenstingl1-1/+1
2017-04-07clk: meson: mpll: fix division by zero in rate_from_paramsMartin Blumenstingl1-11/+15