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path: root/drivers/clk/meson
AgeCommit message (Expand)AuthorFilesLines
2023-01-13clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rateMartin Blumenstingl1-5/+4
2023-01-13clk: meson: sclk-div: switch from .round_rate to .determine_rateMartin Blumenstingl1-5/+6
2023-01-13clk: meson: dualdiv: switch from .round_rate to .determine_rateMartin Blumenstingl1-8/+13
2023-01-13clk: meson: mpll: Switch from .round_rate to .determine_rateMartin Blumenstingl1-7/+13
2022-12-12Merge branches 'clk-bindings', 'clk-renesas', 'clk-amlogic', 'clk-allwinner' ...Stephen Boyd1-8/+12
2022-11-23clk: Remove a useless includeChristophe JAILLET1-1/+0
2022-11-08clk: meson: pll: add pcie lock retry workaroundHeiner Kallweit1-4/+8
2022-11-08clk: meson: pll: adjust timeout in meson_clk_pll_wait_lock()Heiner Kallweit1-4/+4
2022-08-20clk: meson: Hold reference returned by of_get_parent()Liang He3-3/+12
2022-06-16clk: meson: axg-audio: Don't duplicate devm_clk_get_enabled()Uwe Kleine-König1-32/+4
2022-03-12clk: cleanup commentsTom Rix1-1/+1
2021-11-30clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBBMartin Blumenstingl1-3/+41
2021-09-23clk: meson: meson8b: Make the video clock trees mutableMartin Blumenstingl1-38/+38
2021-09-23clk: meson: meson8b: Initialize the HDMI PLL registersMartin Blumenstingl2-5/+48
2021-09-23clk: meson: meson8b: Add the HDMI PLL M/N parametersMartin Blumenstingl1-0/+22
2021-09-23clk: meson: meson8b: Add the vid_pll_lvds_en gate clockMartin Blumenstingl2-2/+24
2021-09-23clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_selMartin Blumenstingl1-2/+2
2021-09-23clk: meson: meson8b: Export the video clocksMartin Blumenstingl1-11/+1
2021-06-30clk: meson: regmap: switch to determine_rate for the dividersMartin Blumenstingl1-10/+9
2021-06-09clk: meson: g12a: Add missing NNA source clocks for g12bNick Xie1-0/+6
2021-05-24clk: meson: axg-audio: improve deferral handlingJerome Brunet1-3/+2
2021-05-20clk: meson: g12a: fix gp0 and hifi rangesJerome Brunet1-1/+1
2021-05-19clk: meson: pll: switch to determine_rate for the PLL opsMartin Blumenstingl1-11/+15
2021-02-09clk: meson: axg: Remove MIPI enable clock gateRemi Pommarel2-4/+0
2021-01-04clk: meson: meson8b: remove compatibility code for old .dtbsMartin Blumenstingl1-40/+5
2021-01-04clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()Martin Blumenstingl1-2/+3
2021-01-04clk: meson: clk-pll: make "ret" a signed integerMartin Blumenstingl1-1/+2
2021-01-04clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLLMartin Blumenstingl1-1/+1
2020-12-21Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds11-61/+1004
2020-11-26clk: meson: g12a: add MIPI DSI Host Pixel ClockNeil Armstrong2-1/+76
2020-11-23clk: meson: enable building as modulesKevin Hilman9-9/+34
2020-11-23clk: meson: Kconfig: fix dependency for G12AKevin Hilman1-0/+1
2020-11-23clk: meson: axg: add MIPI DSI Host clockNeil Armstrong2-1/+69
2020-11-23clk: meson: axg: add Video ClocksNeil Armstrong2-1/+773
2020-11-14clk: meson: g12: use devm variant to register notifiersJerome Brunet1-14/+20
2020-11-14clk: meson: g12: drop use of __clk_lookup()Jerome Brunet1-36/+32
2020-10-29clk: define to_clk_regmap() as inline functionArnd Bergmann1-1/+4
2020-10-20Merge branches 'clk-semicolon', 'clk-axi-clkgen', 'clk-qoriq', 'clk-baikal', ...Stephen Boyd1-1/+1
2020-10-14clk: meson: use semicolons rather than commas to separate statementsJulia Lawall1-1/+1
2020-09-10clk: meson: make shipped controller configurableJerome Brunet1-9/+17
2020-08-29clk: meson: g12a: mark fclk_div2 as criticalStefan Agner1-0/+11
2020-08-17clk: meson: axg-audio: fix g12a tdmout sclk inverterJerome Brunet1-25/+60
2020-08-17clk: meson: axg-audio: separate axg and g12a regmap tablesJerome Brunet1-8/+127
2020-08-17clk: meson: add sclk-ws driverJerome Brunet2-0/+62
2020-07-21Merge branch 'clk-amlogic' into clk-nextStephen Boyd4-19/+178
2020-07-11Replace HTTP links with HTTPS ones: Common CLK frameworkAlexander A. Klimov1-1/+1
2020-07-09clk: meson: meson8b: add the vclk2_en gate clockMartin Blumenstingl2-6/+27
2020-07-09clk: meson: meson8b: add the vclk_en gate clockMartin Blumenstingl2-6/+27
2020-06-24clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2Martin Blumenstingl1-7/+0
2020-06-19clk: meson: g12a: Add support for NNA CLK source clocksDmitry Shmidt2-1/+125