summaryrefslogtreecommitdiff
path: root/drivers/clk/meson
AgeCommit message (Expand)AuthorFilesLines
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2-0/+2
2019-05-07Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and 'clk-basic-be'...Stephen Boyd9-516/+2171
2019-04-08clk: meson: axg-audio: add g12a supportMaxime Jourdan2-8/+239
2019-04-08clk: meson: axg-audio: don't register inputs in the onecell dataJerome Brunet2-44/+6
2019-04-08clk: meson: axg_audio: replace prefix axg by audJerome Brunet1-482/+482
2019-04-01clk: meson: meson8b: add the video decoder clock treesMartin Blumenstingl2-1/+328
2019-04-01clk: meson: meson8b: add the VPU clock treesMartin Blumenstingl2-1/+175
2019-04-01clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2Martin Blumenstingl2-1/+66
2019-04-01clk: meson: meson8b: use a separate clock table for Meson8m2Martin Blumenstingl1-1/+192
2019-04-01clk: meson-g12a: add video decoder clocksMaxime Jourdan2-1/+170
2019-04-01clk: meson-g12a: add PCIE PLL clocksNeil Armstrong2-1/+122
2019-04-01clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLLNeil Armstrong2-0/+27
2019-04-01clk: meson: g12a: add cpu clocksNeil Armstrong2-1/+371
2019-04-01dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCINNeil Armstrong1-1/+0
2019-04-01dt-bindings: clock: axg-audio: unexpose controller inputsJerome Brunet1-0/+20
2019-03-29clk: meson: vid-pll-div: remove warning and return 0 on invalid configNeil Armstrong1-2/+2
2019-03-25clk: meson: pll: fix rounding and setting a rate that matches preciselyMartin Blumenstingl1-1/+1
2019-03-19clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock idNeil Armstrong1-1/+0
2019-03-19clk: meson-g12a: fix VPU clock parentsNeil Armstrong1-1/+1
2019-03-19clk: meson: g12a: fix VPU clock muxes maskMaxime Jourdan1-2/+2
2019-03-19clk: meson-gxbb: round the vdec dividers to closestMaxime Jourdan1-0/+2
2019-02-13clk: meson: meson8b: fix the naming of the APB clocksMartin Blumenstingl2-14/+14
2019-02-13clk: meson: Add G12A AO Clock + Reset ControllerNeil Armstrong4-1/+491
2019-02-04clk: meson: factorise meson64 peripheral clock controller driversJerome Brunet7-176/+313
2019-02-04clk: meson: g12a: add peripheral clock controllerJian Hu5-2/+2594
2019-02-04clk: meson: pll: update driver for the g12aJerome Brunet2-59/+154
2019-02-02clk: meson: rework and clean drivers dependenciesJerome Brunet29-281/+465
2019-02-02clk: meson: axg-audio does not require sysconJerome Brunet1-1/+1
2019-01-18clk: meson: ao-clkc: claim clock controller input clocks from DTJerome Brunet4-14/+82
2019-01-18clk: meson: axg: claim clock controller input clock from DTJerome Brunet1-8/+19
2019-01-18clk: meson: gxbb: claim clock controller input clock from DTJerome Brunet1-13/+24
2019-01-07clk: meson: meson8b: add the GPU clock treeMartin Blumenstingl2-1/+154
2019-01-07clk: meson: meson8b: use a separate clock table for Meson8Martin Blumenstingl1-6/+197
2019-01-07clk: meson: axg-ao: add 32k generation subtreeJerome Brunet2-25/+163
2019-01-07clk: meson: gxbb-ao: replace cec-32k with the dual dividerJerome Brunet4-262/+204
2019-01-07clk: meson: add dual divider clock driverJerome Brunet3-1/+150
2019-01-07clk: meson: clean-up clock registrationJerome Brunet1-5/+10
2018-12-15Merge branch 'clk-fixes' into clk-nextStephen Boyd2-0/+25
2018-12-13Merge tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson into cl...Stephen Boyd7-71/+870
2018-12-11clk: meson: axg-audio: use the clk input helper functionJerome Brunet1-59/+24
2018-12-05clk: meson: add clk-input helper functionJerome Brunet3-0/+50
2018-12-04clk: meson: Mark some things staticStephen Boyd2-6/+6
2018-12-03clk: meson: meson8b: add the read-only video clock treesMartin Blumenstingl2-10/+782
2018-12-03clk: meson: meson8b: add the fractional divider for vid_pll_dcoMartin Blumenstingl2-0/+6
2018-12-03clk: meson: meson8b: fix the offset of vid_pll_dco's N valueMartin Blumenstingl1-1/+1
2018-11-27clk: meson: Fix GXL HDMI PLL fractional bits widthNeil Armstrong1-1/+7
2018-11-23clk: meson: meson8b: add the CPU clock post divider clocksMartin Blumenstingl2-1/+256
2018-11-23clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3Martin Blumenstingl2-12/+12
2018-11-23clk: meson: clk-regmap: add read-only gate opsMartin Blumenstingl2-0/+6
2018-11-23clk: meson: meson8b: allow changing the CPU clock treeMartin Blumenstingl1-6/+6