summaryrefslogtreecommitdiff
path: root/drivers/clk/qcom/clk-alpha-pll.h
AgeCommit message (Collapse)AuthorFilesLines
2024-02-06clk: qcom: clk-alpha-pll: Add support for zonda ole pll configureRajendra Nayak1-0/+4
Zonda ole pll has as extra PLL_OFF_CONFIG_CTL_U2 register, hence add support for it. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-6-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-10-21clk: qcom: clk-alpha-pll: introduce stromer plus opsVaradarajan Narayanan1-0/+1
Stromer plus APSS PLL does not support dynamic frequency scaling. To switch between frequencies, we have to shut down the PLL, configure the L and ALPHA values and turn on again. So introduce the separate set of ops for Stromer Plus PLL. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/2affa6c63ff0c4342230623a7d4eef02ec7c02d4.1697781921.git.quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-19clk: qcom: clk-alpha-pll: Add support for lucid ole pll configureJagadeesh Kona1-0/+2
Lucid ole pll has as extra RINGOSC_CAL_L field in L register in addition to the fields that are part of lucid evo pll, hence add support for lucid ole pll configure function to configure the ole plls. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230707035744.22245-3-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-06-14clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi)Konrad Dybcio1-0/+2
The "vanilla" Alpha PLL configs are sometimes provided with an intention to only update certain bits of th register. Do so if a mask is found. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Iskren Chernev <me@iskren.info> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230601-topic-alpha_ctl-v1-1-b6a932dfcf68@linaro.org
2023-05-25clk: qcom: clk-alpha-pll: Add support to configure PLL_TEST_CTL_U2Jagadeesh Kona1-0/+1
The lucid ole pll reuses lucid evo ops but it has an additional test control register which is required to be programmed, add support to program the same. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230524145203.13153-2-quic_jkona@quicinc.com
2023-03-16clk: qcom: Add STROMER PLUS PLL type for IPQ5332Kathiravan T1-0/+1
Add the support for stromer plus pll, which is found on the IPQ5332 SoCs. Programming sequence is same as the stromer pll, so we can re-use the same. Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230307062232.4889-3-quic_kathirav@quicinc.com
2023-03-16clk: qcom: clk-alpha-pll: Add support for Stromer PLLsVaradarajan Narayanan1-1/+12
Add programming sequence support for managing the Stromer PLLs. Reviewed-by: Stephen Boyd <sboyd@kernel.org> Co-developed-by: Sricharan R <quic_srichara@quicinc.com> Signed-off-by: Sricharan R <quic_srichara@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230307062232.4889-2-quic_kathirav@quicinc.com
2023-01-10clk: qcom: clk-alpha-pll: define alias of LUCID OLE reset ops to EVO reset opsNeil Armstrong1-0/+1
Add an alias of LUCID OLE reset ops to EVO reset ops similar to other aliases. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103-topic-sm8550-upstream-dispcc-v3-2-8a03d348c572@linaro.org
2022-12-02clk: qcom: Add LUCID_OLE PLL type for SM8550Abel Vesa1-0/+5
Add a LUCID_OLE PLL type for SM8550 SoC from Qualcomm. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221130112852.2977816-5-abel.vesa@linaro.org
2022-09-28clk: qcom: alpha: Add support for programming the PLL_FSM_LEGACY_MODE bitKonrad Dybcio1-2/+3
This is used on at least SM6375 and its variations. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220921001303.56151-1-konrad.dybcio@somainline.org
2022-09-27clk: qcom: Merge alt alpha plls for qcm2260, sm6115Iskren Chernev1-0/+2
The qcom2260 and sm6115 GCC drivers use a common modified DEFAULT and BRAMMO alpha pll offsets. Move these common offsets to the shared place to avoid duplication. The new layouts have a suffix EVO similar to LUCID and RIVIAN. Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220830075620.974009-4-iskren.chernev@gmail.com
2022-09-27clk: qcom: alpha-pll: add support for power off mode for lucid evo PLLDmitry Baryshkov1-0/+1
PLLs can be kept in standby (default configuration) or in off mode when disabled during power collapse. Hence add support for pll disable off mode for lucid evo PLL. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220908222850.3552050-3-dmitry.baryshkov@linaro.org
2022-07-06clk: qcom: clk-alpha-pll: add Rivian EVO PLL configuration interfacesVladimir Zapolskiy1-0/+6
Add and export Rivian EVO PLL configuration and control functions to clock controller drivers, the PLL is used by SM8450 camera clock controller. Reviewed-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220701062739.2757912-1-vladimir.zapolskiy@linaro.org
2022-07-06clk: qcom: clk-alpha-pll: add Lucid EVO PLL configuration interfacesVladimir Zapolskiy1-1/+4
Add controls for Lucid EVO PLL configuration and export control functions to clock controller drivers, the PLL is used by Qualcomm SM8450 camera and display clock controllers. Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220701062729.2757893-1-vladimir.zapolskiy@linaro.org
2021-12-16clk: qcom: Add LUCID_EVO PLL type for SDX65Vamsi Krishna Lanka1-0/+3
Add a LUCID_EVO PLL type for SDX65 SoC from Qualcomm. Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> [bjorn: Fixed indentation issues reported by checkpatch] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/d582c3e291ae82aa488785eff36157653741f841.1638861860.git.quic_vamslank@quicinc.com
2021-06-28clk: qcom: clk-alpha-pll: add support for zonda pllJonathan Marek1-0/+6
Ported over from the downstream driver. Will be used by SM8250 CAMCC. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20210609022051.2171-2-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: clk-alpha-pll: Add support for Lucid 5LPE PLLVivek Aknurwar1-0/+4
Lucid 5LPE is a slightly different Lucid PLL with different offsets and porgramming sequence so add support for these Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org> Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org> [vkoul: rebase and tidy up for upstream] Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210127070811.152690-4-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-05clk: qcom: clk-alpha-pll: Add support for controlling Agera PLLsTaniya Das1-0/+4
Add programming sequence support for managing the Agera PLLs. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1602873815-1677-3-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24clk: qcom: clk-alpha-pll: use the right PCAL_DONE value for lucid pllJonathan Marek1-1/+1
Lucid PCAL_DONE is different from trion. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200709135251.643-5-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24clk: qcom: clk-alpha-pll: same regs and ops for trion and lucidJonathan Marek1-6/+11
Fixed ops were already identical, this adds support for non-fixed ops by sharing between trion and lucid. This also changes the names for trion ops to be consistent with the rest. Note LUCID_PCAL_DONE is renamed to TRION_PCAL_DONE because it is wrong for lucid, LUCID_PCAL_DONE should be BIT(27). Next patch will address this. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200709135251.643-4-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-11clk: qcom: Add CPU clock driver for msm8996Loic Poulain1-0/+6
Each of the CPU clusters (Power and Perf) on msm8996 are clocked via 2 PLLs, a primary and alternate. There are also 2 Mux'es, a primary and secondary all connected together as shown below +-------+ XO | | +------------------>0 | | | PLL/2 | SMUX +----+ +------->1 | | | | | | | +-------+ | +-------+ | +---->0 | | | | +---------------+ | +----------->1 | CPU clk |Primary PLL +----+ PLL_EARLY | | +------> | +------+-----------+ +------>2 PMUX | +---------------+ | | | | | +------+ | +-->3 | +--^+ ACD +-----+ | +-------+ +---------------+ +------+ | |Alt PLL | | | +---------------------------+ +---------------+ PLL_EARLY The primary PLL is what drives the CPU clk, except for times when we are reprogramming the PLL itself (for rate changes) when we temporarily switch to an alternate PLL. A subsequent patch adds support to switch between primary and alternate PLL during rate changes. The primary PLL operates on a single VCO range, between 600MHz and 3GHz. However the CPUs do support OPPs with frequencies between 300MHz and 600MHz. In order to support running the CPUs at those frequencies we end up having to lock the PLL at twice the rate and drive the CPU clk via the PLL/2 output and SMUX. So for frequencies above 600MHz we follow the following path Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk and for frequencies between 300MHz and 600MHz we follow Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk ACD stands for Adaptive Clock Distribution and is used to detect voltage droops. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Rajendra Nayak: Initial RFC - https://lkml.org/lkml/2016/9/29/84 Signed-off-by: Ilia Lin <ilialin@codeaurora.org> Ilia Lin: - reworked clock registering - Added clock-tree diagram - non-builtin support - clock notifier on rate change - https://lkml.org/lkml/2018/5/24/123 Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Loic Poulain: - fixed driver remove / clk deregistering - Removed useless memory barriers - devm usage when possible - Fixed Kconfig depends Link: https://lore.kernel.org/r/1593766185-16346-3-git-send-email-loic.poulain@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-10clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLsTaniya Das1-0/+12
Add programming sequence support for managing the Lucid PLLs. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lkml.kernel.org/r/20200224045003.3783838-4-vkoul@kernel.org Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-24clk: qcom: clk-alpha-pll: Add support for Fabia PLL calibrationTaniya Das1-0/+4
In the cases where the PLL is not calibrated the PLL could fail to lock. Add support for prepare ops which would take care of the same. Fabia PLL user/test control registers might required to be configured, so add support for configuring them. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1573812304-24074-3-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-19clk: qcom: gcc: limit GPLL0_AO_OUT operating frequencyJorge Ramirez-Ortiz1-0/+1
Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware specifications. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20191125135910.679310-3-niklas.cassel@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-08clk: qcom: clk-alpha-pll: Add support for Trion PLLsDeepak Katragadda1-0/+7
Add programming sequence support for managing the Trion PLLs. Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> [vkoul: port to upstream and tidy-up use upstream way of specifying PLLs] Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lkml.kernel.org/r/20190722074348.29582-4-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-25clk: qcom: Update SPDX headers for common filesTaniya Das1-12/+2
SPDX headers updated for common/branch/pll/regmap files. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20clk: qcom: Add support for controlling Fabia PLLAmit Nischal1-1/+17
Fabia PLL is a Digital Frequency Locked Loop (DFLL) clock generator which has a wide range of frequency output. It supports dynamic updating of the output frequency ("frequency slewing") without need to turn off the PLL before configuration. Add support for initial configuration and programming sequence to control fabia PLLs. Signed-off-by: Amit Nischal <anischal@codeaurora.org> [sboyd: Shorten code a little] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2017-12-14clk: qcom: add read-only alpha pll post divider operationsAbhishek Sahu1-0/+1
Some of the divider settings are preconfigured and should not be changed by the clock framework during frequency change. This patch adds the read-only divider operation for QCOM alpha pll post divider which is equivalent to generic divider operations in 'commit 79c6ab509558 ("clk: divider: add CLK_DIVIDER_READ_ONLY flag")'. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-14clk: qcom: support Brammo type Alpha PLLAbhishek Sahu1-0/+1
The Brammo type of Alpha PLL doesn't allow configuration of a VCO, but it does support dynamic update in which the frequency can be changed dynamically without turning off the PLL. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-14clk: qcom: support Huayra type Alpha PLLAbhishek Sahu1-0/+2
The Huayra type Alpha PLL has a 16 bit alpha value, and depending on the alpha_mode, the alpha value can be treated as M/N value or as a two’s compliment number. This PLL supports dynamic programming. Since the decoding of alpha val and dynamic programming are completely different from other Alpha PLLs we add separate functions for Huayra PLLs. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-14clk: qcom: support for dynamic updating the PLLAbhishek Sahu1-0/+1
Some of the Alpha PLLs support dynamic update in which the frequency can be changed dynamically without turning off the PLL. This dynamic update requires the following sequence: 1. Write the desired values to L_VAL and ALPHA_VAL registers 2. Toggle pll_latch_input from low to high 3. Wait for pll_ack_latch to transition from low to high The new L and alpha values have been latched. It may take some time for the PLL to fully settle with these new values. 4. Pull pll_latch_input low Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-14clk: qcom: support for alpha mode configurationAbhishek Sahu1-0/+3
The current configuration does not fully configure PLL alpha mode and values so this patch 1. Configures PLL_ALPHA_VAL_U for PLL which supports 40 bit alpha. 2. Adds alpha enable and alpha mode configuration support. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-14clk: qcom: fix 16 bit alpha support calculationAbhishek Sahu1-1/+0
The alpha value calculation has been written for 40-bit alpha values which doesn't work work properly for 16-bit ones. The alpha value is calculated on the basis of ALPHA_BITWIDTH to make the computation easy for 40 bit alpha. After calculating the 32 bit alpha, it is converted to 40 bit alpha by making lower bits zero. But if actual alpha register width is less than ALPHA_BITWIDTH, then the actual width can be used for calculation. This also means, during the 40 bit alpha pll set rate path, the lower alpha register is not configured Change the code to calculate the rate and register values from 'alpha_width' instead of hard-coding it so that it can work for the different widths that are supported. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-14clk: qcom: support for alpha pll propertiesAbhishek Sahu1-0/+26
Alpha PLL is a generic name used for QCOM PLLs which uses L and Alpha values for configuring the integer and fractional part. QCOM SoCs use different types of Alpha PLLs for which basic software configuration part is common with following differences. 1. All these PLLs have the same basic registers like PLL_MODE, L_VAL, ALPHA_VAL but some of the register offsets are different between PLLs types. 2. The dynamic programming sequence is different in some of the Alpha PLLs 3. Some of the PLLs don’t have 64 bit config control, 64 bit user control, VCO configuration, etc. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: qcom: Enable FSM mode for votable alpha PLLsRajendra Nayak1-0/+1
The votable alpha PLLs need to have the fsm mode enabled as part of the initialization. The sequence seems to be the same as used by clk-pll, so move the function which does this into a common place and reuse it for the clk-alpha-pll Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: qcom: handle alpha PLLs with 16bit alpha val registersRajendra Nayak1-0/+1
Some alpha PLLs have support for only a 16bit programable Alpha Value (as against the default 40bits). Add a flag to handle the 16bit alpha registers Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: qcom: Add support to initialize alpha pllsRajendra Nayak1-0/+20
Add a function to do initial configuration of the alpha plls Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02clk: qcom: Add support for alpha pll hwfsm opsRajendra Nayak1-0/+3
Some PLLs can support an HW FSM mode (different from the Votable FSMs, though its the same bit used to enable Votable FSMs as well as HW FSMs) which enables the HW to do the bypass/reset/enable-output-ctrl sequence on its own. So all thats needed from SW is to set the FSM_ENA bit. PLL_ACTIVE_FLAG is whats used to check if the PLL is active/enabled. Some of the PLLs which support HW FSM can also need an OFFLINE request that needs to be toggled across the enable/disable. We use a flag to identify such cases and handle them. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-12-01clk: qcom: Add Alpha PLL supportStephen Boyd1-0/+57
Add support for configuring rates of, enabling, and disabling Alpha PLLs. This is sufficient for the types of PLLs found in the global and multimedia clock controllers. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-28 16:09:14 +0300