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path: root/drivers/clk/renesas/r8a7795-cpg-mssr.c
AgeCommit message (Expand)AuthorFilesLines
2023-09-26clk: renesas: r8a7795: Constify r8a7795_*_clksMarek Vasut1-2/+2
2023-08-15clk: renesas: rcar-gen3: Add ADG clocksKuninori Morimoto1-0/+1
2023-07-27clk: renesas: r8a7795: Add 3DGE and ZG supportGeert Uytterhoeven1-0/+2
2023-02-10clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*Wolfram Sang1-116/+10
2022-04-13clk: renesas: Move RPC core clocksGeert Uytterhoeven1-5/+4
2021-11-19clk: renesas: rcar-gen3: Add SDnH clockWolfram Sang1-4/+8
2021-10-15clk: renesas: r8a779[56]x: Add MLP clocksAndrey Gusakov1-0/+1
2021-03-12clk: renesas: r8a7795: Add TMU clocksNiklas Söderlund1-0/+6
2020-06-22clk: renesas: rcar-gen3: Mark RWDT clocks as criticalUlrich Hecht1-1/+1
2020-02-10clk: renesas: r8a7795: Add RPC clocksDirk Behme1-0/+8
2019-06-18clk: renesas: r8a7795: Add CMM clocksJacopo Mondi1-0/+4
2019-05-21clk: renesas: r8a779{5|6|65}: Add TPU clockCao Van Dong1-0/+1
2019-04-02clk: renesas: rcar-gen3: Rename DRIF clocksTakeshi Kihara1-9/+9
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of Audio-DMACTakeshi Kihara1-2/+2
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of SYS-DMACTakeshi Kihara1-2/+2
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of HS-USBKazuya Mizuguchi1-2/+2
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCIKazuya Mizuguchi1-4/+4
2019-04-02clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2Simon Horman1-1/+1
2019-04-02clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offsetSimon Horman1-2/+2
2019-04-02clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisorTakeshi Kihara1-2/+3
2018-12-04clk: renesas: r8a7795: Add CPEX clockGeert Uytterhoeven1-0/+1
2018-10-19Merge branch 'clk-renesas' into clk-nextStephen Boyd1-33/+34
2018-08-31clk: renesas: use SPDX identifier for Renesas driversWolfram Sang1-4/+1
2018-08-27clk: renesas: r8a7795: Add OSC EXTAL predivider configurationGeert Uytterhoeven1-33/+33
2018-08-27clk: renesas: rcar-gen3: Rename rint to .rGeert Uytterhoeven1-1/+2
2018-06-19clk: renesas: r8a7795: Add CCREE clockGilad Ben-Yossef1-0/+1
2018-06-19clk: renesas: r8a7795: Add CR clockGeert Uytterhoeven1-0/+1
2018-02-12clk: renesas: r8a7795: Add Z2 clockTakeshi Kihara1-0/+1
2018-02-12clk: renesas: r8a7795: Add Z clockTakeshi Kihara1-0/+1
2017-10-16clk: renesas: r8a7795: Correct parent clock of INTC-APGeert Uytterhoeven1-1/+2
2017-08-16clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3Geert Uytterhoeven1-17/+17
2017-05-15clk: renesas: r8a7795: Correct pwm, gpio, and i2c parent clocks on ES2.0Geert Uytterhoeven1-13/+26
2017-05-15clk: renesas: r8a7795: Add HS-USB ch3 clockTakeshi Kihara1-0/+1
2017-05-15clk: renesas: r8a7795: Add USB-DMAC ch3 clockTakeshi Kihara1-0/+2
2017-05-15clk: renesas: r8a7795: Add EHCI/OHCI ch3 clockTakeshi Kihara1-0/+1
2017-03-30clk: renesas: r8a7795: Add support for R-Car H3 ES2.0Geert Uytterhoeven1-50/+151
2017-03-21clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()Geert Uytterhoeven1-1/+1
2017-03-21clk: renesas: r8a7795: Reformat core clock tableGeert Uytterhoeven1-10/+10
2017-03-21clk: renesas: r8a7795: Correct name of watchdog clockGeert Uytterhoeven1-1/+1
2017-03-21clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACsGeert Uytterhoeven1-2/+2
2017-03-06clk: renesas: r8a7795: Add IMR clocksSergei Shtylyov1-0/+4
2017-01-27clk: renesas: r8a7795: Add IIC-DVFS clockKeita Kobayashi1-0/+1
2016-11-07clk: renesas: r8a7795: Fix HDMI parent clockTakeshi Kihara1-1/+1
2016-11-02clk: renesas: r8a7795: Obtain mode pin values from R-Car RST driverGeert Uytterhoeven1-1/+7
2016-09-14Merge tag 'clk-renesas-for-v4.9-tag3' of git://git.kernel.org/pub/scm/linux/k...Stephen Boyd1-0/+4
2016-09-12clk: renesas: r8a7795: Add CMT clocksBui Duc Phuc1-0/+4
2016-08-12clk: renesas: r8a7795: Fix SD clocksYoshihiro Shimoda1-4/+5
2016-06-21clk: renesas: r8a7795: Add THS/TSC clockKhiem Nguyen1-0/+1
2016-06-21clk: renesas: r8a7795: Add DRIF clockRamesh Shanmugasundaram1-0/+8
2016-06-21clk: renesas: r8a7795: Correct lvds clock parentGeert Uytterhoeven1-1/+1