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path: root/drivers/clk/renesas/r8a77995-cpg-mssr.c
AgeCommit message (Expand)AuthorFilesLines
2023-08-15clk: renesas: rcar-gen3: Add ADG clocksKuninori Morimoto1-0/+1
2023-03-06clk: renesas: r8a77995: Fix VIN parent clockGeert Uytterhoeven1-1/+1
2022-04-13clk: renesas: Move RPC core clocksGeert Uytterhoeven1-6/+4
2022-04-11clk: renesas: r8a77995: Add RPC clocksGeert Uytterhoeven1-0/+9
2022-01-24clk: renesas: r8a7799[05]: Add MLP clocksNikita Yushchenko1-0/+1
2021-11-19clk: renesas: rcar-gen3: Add SDnH clockWolfram Sang1-1/+2
2021-05-27clk: renesas: r8a77995: Add ZA2 clockKuninori Morimoto1-0/+1
2020-12-28clk: renesas: r8a77995: Add TMU clocksNiklas Söderlund1-0/+5
2020-06-22clk: renesas: rcar-gen3: Mark RWDT clocks as criticalUlrich Hecht1-1/+1
2020-02-10clk: renesas: rcar-gen3: Add CCREE clocksGeert Uytterhoeven1-0/+2
2019-06-18clk: renesas: r8a77995: Add CMM clocksJacopo Mondi1-0/+2
2019-04-02clk: renesas: rcar-gen3: Correct parent clock of Audio-DMACTakeshi Kihara1-1/+1
2018-12-04clk: renesas: r8a77995: Simplify PLL3 multiplier/dividerGeert Uytterhoeven1-2/+2
2018-12-04clk: renesas: r8a77995: Add missing CPEX clockGeert Uytterhoeven1-1/+2
2018-12-04clk: renesas: r8a77995: Remove non-existent SSP clocksGeert Uytterhoeven1-1/+0
2018-12-04clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocksGeert Uytterhoeven1-3/+0
2018-12-04clk: renesas: r8a77995: Correct parent clock of DUGeert Uytterhoeven1-2/+2
2018-10-19Merge branch 'clk-renesas' into clk-nextStephen Boyd1-2/+10
2018-08-31clk: renesas: use SPDX identifier for Renesas driversWolfram Sang1-4/+1
2018-08-27clk: renesas: r8a77995: Correct RCLK handlingGeert Uytterhoeven1-2/+10
2017-10-16clk: renesas: r8a77995: Correct parent clock of INTC-APGeert Uytterhoeven1-1/+1
2017-08-16clk: renesas: cpg-mssr: Add R8A77995 supportGeert Uytterhoeven1-0/+236