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path: root/drivers/clk/renesas
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2024-06-12clk: renesas: r9a07g043: Add clock and reset entry for PLICLad Prabhakar1-0/+9
2024-06-12clk: renesas: r8a779a0: Fix CANFD parent clockGeert Uytterhoeven1-1/+1
2024-03-27clk: renesas: r8a779f0: Correct PFC/GPIO parent clockGeert Uytterhoeven1-1/+1
2024-03-27clk: renesas: r8a779g0: Correct PFC/GPIO parent clocksGeert Uytterhoeven1-5/+6
2024-01-26clk: renesas: rzg2l: Check reset monitor registersClaudiu Beznea1-15/+44
2024-01-26clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset()Claudiu Beznea1-23/+15
2023-11-20clk: renesas: rzg2l: Fix computation formulaClaudiu Beznea1-6/+6
2023-11-20clk: renesas: rzg2l: Use FIELD_GET() for PLL register fieldsClaudiu Beznea1-5/+5
2023-11-20clk: renesas: rzg2l: Trust value returned by hardwareClaudiu Beznea1-7/+1
2023-11-20clk: renesas: rzg2l: Lock around writes to mux registerClaudiu Beznea2-11/+14
2023-11-20clk: renesas: rzg2l: Wait for status bit of SD mux before continuingClaudiu Beznea1-7/+10
2023-11-20clk: renesas: rcar-gen3: Extend SDnH divider tableDirk Behme1-1/+14
2023-08-31Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'c...Stephen Boyd17-19/+73
2023-08-15clk: renesas: rcar-gen3: Add ADG clocksKuninori Morimoto9-1/+9
2023-07-27clk: renesas: r8a77965: Add 3DGE and ZG supportGeert Uytterhoeven1-0/+2
2023-07-27clk: renesas: r8a7796: Add 3DGE and ZG supportGeert Uytterhoeven1-0/+2
2023-07-27clk: renesas: r8a7795: Add 3DGE and ZG supportGeert Uytterhoeven1-0/+2
2023-07-27clk: renesas: emev2: Remove obsolete clkdev registrationGeert Uytterhoeven1-3/+0
2023-07-25clk: renesas: r9a07g043: Add MTU3a clock and reset entryBiju Das1-0/+3
2023-07-19clk: Explicitly include correct DT includesRob Herring3-4/+1
2023-07-11clk: renesas: rzg2l: Simplify .determine_rate()Christophe JAILLET1-7/+1
2023-07-10clk: renesas: r9a09g011: Add CSI related clocksFabrizio Castro1-0/+15
2023-07-10clk: renesas: r8a774b1: Add 3DGE and ZG supportAdam Ford1-0/+2
2023-07-10clk: renesas: r8a774e1: Add 3DGE and ZG supportAdam Ford1-0/+2
2023-07-10clk: renesas: r8a774a1: Add 3DGE and ZG supportAdam Ford1-0/+2
2023-07-10clk: renesas: rcar-gen3: Add support for ZG clockAdam Ford2-4/+32
2023-06-26Merge branches 'clk-renesas', 'clk-determine-rate', 'clk-allwinner', 'clk-sam...Stephen Boyd6-49/+27
2023-06-09clk: renesas: r9a06g032: Add a determine_rate hookMaxime Ripard1-0/+1
2023-06-05clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic()Geert Uytterhoeven1-11/+5
2023-06-05clk: renesas: mstp: Convert to readl_poll_timeout_atomic()Geert Uytterhoeven1-11/+7
2023-06-05clk: renesas: cpg-mssr: Convert to readl_poll_timeout_atomic()Geert Uytterhoeven1-20/+11
2023-05-23clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register writeBiju Das2-7/+2
2023-05-08clk: renesas: r8a779a0: Add PWM clockWolfram Sang1-0/+1
2023-04-30Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds7-204/+591
2023-04-13clk: renesas: remove MODULE_LICENSE in non-modulesNick Alcock2-2/+0
2023-03-30clk: renesas: r8a77980: Add I2C5 clockNikita Yushchenko1-0/+1
2023-03-16clk: renesas: Convert to platform remove callback returning voidUwe Kleine-König1-4/+2
2023-03-10clk: renesas: r9a06g032: Improve clock tablesRalph Siemsen1-153/+407
2023-03-10clk: renesas: r9a06g032: Document structsRalph Siemsen1-1/+49
2023-03-10clk: renesas: r9a06g032: Drop unused fieldsRalph Siemsen1-5/+10
2023-03-10clk: renesas: r9a06g032: Improve readabilityRalph Siemsen1-41/+80
2023-03-10clk: renesas: r8a77980: Add Z2 clockGeert Uytterhoeven1-0/+1
2023-03-10clk: renesas: r8a77970: Add Z2 clockGeert Uytterhoeven1-0/+1
2023-03-06clk: renesas: r8a77995: Fix VIN parent clockGeert Uytterhoeven1-1/+1
2023-03-06clk: renesas: r8a77980: Add VIN clocksNiklas Söderlund1-0/+16
2023-03-06clk: renesas: r8a779g0: Add VIN clocksNiklas Söderlund1-0/+16
2023-03-06clk: renesas: r8a779g0: Add ISPCS clocksNiklas Söderlund1-0/+2
2023-03-06clk: renesas: r8a779g0: Add CSI-2 clocksNiklas Söderlund1-0/+3
2023-03-06clk: renesas: r8a779g0: Add thermal clockGeert Uytterhoeven1-0/+1
2023-03-06clk: renesas: r8a779g0: Add Audio clocksKuninori Morimoto1-0/+2