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path: root/drivers/clk/renesas
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2017-08-24Merge tag 'clk-renesas-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/...Stephen Boyd12-84/+560
2017-08-17clk: renesas: r8a7796: Add USB3.0 clockHiromitsu Yamasaki1-0/+1
2017-08-17clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHYYoshihiro Shimoda3-0/+194
2017-08-16clk: renesas: cpg-mssr: Add R8A77995 supportGeert Uytterhoeven5-0/+249
2017-08-16clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocksGeert Uytterhoeven2-1/+26
2017-08-16clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3Geert Uytterhoeven4-37/+41
2017-07-22clk: Convert to using %pOF instead of full_nameRob Herring2-3/+2
2017-07-19clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div tableWolfram Sang1-26/+20
2017-07-19clk: renesas: rcar-gen3-cpg: Drop superfluous variableWolfram Sang1-2/+1
2017-07-17clk: renesas: Allow compile-testing of all (sub)driversGeert Uytterhoeven1-19/+19
2017-07-17clk: renesas: r8a7792: Add IMR-LX3/LSX3 clocksGeert Uytterhoeven1-0/+7
2017-07-17clk: renesas: div6: Document fields used for parent selectionGeert Uytterhoeven1-0/+3
2017-06-20clk: renesas: cpg-mssr: Use of_device_get_match_data() helperGeert Uytterhoeven1-1/+1
2017-05-24clk: renesas: r8a7794: Add new CPG/MSSR driverGeert Uytterhoeven5-2/+266
2017-05-24clk: renesas: r8a7792: Add new CPG/MSSR driverGeert Uytterhoeven5-2/+232
2017-05-24clk: renesas: r8a7791/r8a7793: Add new CPG/MSSR driverGeert Uytterhoeven5-2/+302
2017-05-24clk: renesas: r8a7790: Add new CPG/MSSR driverGeert Uytterhoeven5-1/+298
2017-05-24clk: renesas: Rework Kconfig and Makefile logicGeert Uytterhoeven3-36/+134
2017-05-24clk: renesas: cpg-mssr: Initialize error pointer using ERR_PTR()Geert Uytterhoeven1-1/+1
2017-05-15clk: renesas: r8a7795: Correct pwm, gpio, and i2c parent clocks on ES2.0Geert Uytterhoeven1-13/+26
2017-05-15clk: renesas: Use pm_clk_no_clocks() helper i.s.o. direct accessGeert Uytterhoeven2-2/+2
2017-05-15clk: renesas: Do not build clk-div6 for R8A7792Geert Uytterhoeven1-1/+1
2017-05-15clk: renesas: r8a7796: Add INTC-EX clockTakeshi Kihara1-0/+1
2017-05-15clk: renesas: r8a7796: Add PCIe clocksHarunobu Kurokawa1-0/+2
2017-05-15clk: renesas: r8a7796: Add PWM clockRyo Kodama1-0/+1
2017-05-15clk: renesas: r8a7796: Add HS-USB clockKazuya Mizuguchi1-0/+1
2017-05-15clk: renesas: r8a7796: Add Sound DVC clocksKazuya Mizuguchi1-0/+2
2017-05-15clk: renesas: r8a7796: Add Sound SRC clockKazuya Mizuguchi1-0/+13
2017-05-15clk: renesas: r8a7796: Add Sound SSI clockKazuya Mizuguchi1-0/+11
2017-05-15clk: renesas: r8a7796: Add USB-DMAC clocksHiromitsu Yamasaki1-0/+2
2017-05-15clk: renesas: r8a7796: Add Audio-DMAC clocksHiromitsu Yamasaki1-0/+2
2017-05-15clk: renesas: r8a7796: Add EHCI/OHCI clocksKazuya Mizuguchi1-0/+2
2017-05-15clk: renesas: r8a7796: Add HDMI clockKoji Matsuoka1-0/+2
2017-05-15clk: renesas: r8a7795: Add HS-USB ch3 clockTakeshi Kihara1-0/+1
2017-05-15clk: renesas: r8a7795: Add USB-DMAC ch3 clockTakeshi Kihara1-0/+2
2017-05-15clk: renesas: r8a7795: Add EHCI/OHCI ch3 clockTakeshi Kihara1-0/+1
2017-05-15clk: renesas: r8a7745: Remove PLL configs for MD19=0Geert Uytterhoeven1-11/+2
2017-05-15clk: renesas: r8a7745: Remove nonexisting scu-src[0789] clocksGeert Uytterhoeven1-4/+0
2017-05-15clk: renesas: rcar-gen2: Fix PLL0 on R-Car V2H and E2Geert Uytterhoeven1-4/+19
2017-03-30clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0Geert Uytterhoeven1-11/+27
2017-03-30clk: renesas: r8a7795: Add support for R-Car H3 ES2.0Geert Uytterhoeven1-50/+151
2017-03-30clk: renesas: cpg-mssr: Add support for fixing up clock tablesGeert Uytterhoeven2-0/+72
2017-03-21clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0Geert Uytterhoeven1-0/+24
2017-03-21clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()Geert Uytterhoeven4-4/+6
2017-03-21clk: renesas: r8a7796: Reformat core clock tableGeert Uytterhoeven1-6/+6
2017-03-21clk: renesas: r8a7795: Reformat core clock tableGeert Uytterhoeven1-10/+10
2017-03-21clk: renesas: r8a7796: Correct name of watchdog clockGeert Uytterhoeven1-1/+1
2017-03-21clk: renesas: r8a7795: Correct name of watchdog clockGeert Uytterhoeven1-1/+1
2017-03-21clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACsGeert Uytterhoeven1-2/+2
2017-03-06clk: renesas: r8a7796: Add IMR clocksSergei Shtylyov1-0/+2