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path: root/drivers/clk/renesas
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2021-09-03Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds10-26/+87
2021-08-29Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds1-1/+1
2021-08-29clk: renesas: rcar-usb2-clock-sel: Fix kernel NULL pointer dereferenceAdam Ford1-1/+1
2021-08-13clk: renesas: Make CLK_R9A06G032 invisibleGeert Uytterhoeven1-3/+1
2021-07-26clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2Lad Prabhakar1-1/+2
2021-07-19clk: renesas: r9a07g044: Add clock and reset entries for ADCLad Prabhakar1-0/+6
2021-07-19clk: renesas: r9a07g044: Add clock and reset entries for CANFDLad Prabhakar1-0/+4
2021-07-19clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]Geert Uytterhoeven4-3/+3
2021-07-19clk: renesas: r9a07g044: Add GPIO clock and reset entriesLad Prabhakar1-0/+5
2021-07-19clk: renesas: r9a07g044: Add SSIF-2 clock and reset entriesBiju Das1-0/+20
2021-07-19clk: renesas: r9a07g044: Add USB clocks/resetsBiju Das1-0/+12
2021-07-19clk: renesas: r9a07g044: Add DMAC clocks/resetsBiju Das1-0/+8
2021-07-19clk: renesas: r9a07g044: Add I2C clocks/resetsBiju Das1-0/+12
2021-07-19clk: renesas: r8a779a0: Add the DSI clocksKieran Bingham1-1/+3
2021-07-19clk: renesas: r8a779a0: Add the DU clockKieran Bingham1-0/+1
2021-07-19clk: renesas: rzg2: Rename i2c-dvfs to iic-pmicGeert Uytterhoeven4-4/+4
2021-07-19clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get()Lad Prabhakar1-1/+1
2021-07-19clk: renesas: rzg2l: Avoid mixing error pointers and NULLDan Carpenter1-1/+1
2021-07-19clk: renesas: rzg2l: Fix a double free on errorDan Carpenter1-7/+1
2021-07-19clk: renesas: rzg2l: Fix return value and unused assignmentYang Li1-4/+2
2021-07-19clk: renesas: rzg2l: Remove unneeded semicolonYang Li1-1/+1
2021-07-12dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitionsBiju Das3-64/+93
2021-07-12clk: renesas: r9a07g044: Add P2 Clock supportBiju Das2-0/+5
2021-07-12clk: renesas: r9a07g044: Fix P1 ClockBiju Das1-3/+3
2021-07-12clk: renesas: r9a07g044: Rename divider tableBiju Das1-3/+4
2021-07-12clk: renesas: rzg2l: Add multi clock PM supportBiju Das1-22/+29
2021-06-10clk: renesas: Add support for R9A07G044 SoCLad Prabhakar5-0/+141
2021-06-10clk: renesas: Add CPG core wrapper for RZ/G2L SoCLad Prabhakar4-0/+883
2021-05-27clk: renesas: r8a77995: Add ZA2 clockKuninori Morimoto1-0/+1
2021-05-27clk: renesas: cpg-mssr: Make srstclr[] comment block consistentGeert Uytterhoeven1-1/+3
2021-05-27clk: renesas: cpg-mssr: Remove unused [RM]MSTPCR() definitionsGeert Uytterhoeven1-6/+0
2021-05-11clk: renesas: r9a06g032: Switch to .determine_rate()Geert Uytterhoeven1-12/+13
2021-05-11clk: renesas: div6: Implement range checkingGeert Uytterhoeven1-1/+7
2021-05-11clk: renesas: div6: Consider all parents for requested rateGeert Uytterhoeven1-3/+32
2021-05-11clk: renesas: div6: Switch to .determine_rate()Geert Uytterhoeven1-5/+7
2021-05-11clk: renesas: div6: Simplify src mask handlingGeert Uytterhoeven1-20/+11
2021-05-11clk: renesas: div6: Use clamp() instead of clamp_t()Geert Uytterhoeven1-1/+1
2021-05-11clk: renesas: rcar-usb2-clock-sel: Fix error handling in .probe()Dinghao Liu1-9/+15
2021-05-11clk: renesas: r8a779a0: Add ISPCS clocksNiklas Söderlund1-0/+4
2021-05-11clk: renesas: rcar-gen3: Add boost support to Z clocksGeert Uytterhoeven1-4/+20
2021-05-11clk: renesas: rcar-gen3: Add custom clock for PLLsGeert Uytterhoeven1-19/+128
2021-05-11clk: renesas: rcar-gen3: Increase Z clock accuracyGeert Uytterhoeven1-2/+2
2021-05-11clk: renesas: rcar-gen3: Grammar s/dependent of/dependent on/Geert Uytterhoeven1-1/+1
2021-05-11clk: renesas: rcar-gen3: Remove superfluous masking in cpg_z_clk_set_rate()Geert Uytterhoeven1-2/+1
2021-05-11clk: renesas: rcar-gen3: Make cpg_z_clk.mask u32Geert Uytterhoeven1-1/+1
2021-05-11clk: renesas: rcar-gen3: Update Z clock rate formula in commentsGeert Uytterhoeven1-1/+2
2021-03-30clk: renesas: Zero init clk_init_dataGeert Uytterhoeven8-16/+11
2021-03-24clk: renesas: Couple of spelling fixesBhaskar Chowdhury1-2/+2
2021-03-12clk: renesas: r8a779a0: Add CMT clocksWolfram Sang1-0/+4
2021-03-12clk: renesas: r8a7795: Add TMU clocksNiklas Söderlund1-0/+6