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path: root/drivers/clk/renesas
AgeCommit message (Expand)AuthorFilesLines
2023-02-10clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*Wolfram Sang5-173/+13
2023-01-26clk: renesas: r8a779g0: Add CAN-FD clocksGeert Uytterhoeven1-0/+2
2023-01-26clk: renesas: r8a779g0: Tidy up DMAC name on SYS-DMACKuninori Morimoto1-2/+2
2023-01-26clk: renesas: r8a779a0: Tidy up DMAC name on SYS-DMACKuninori Morimoto1-2/+2
2023-01-24clk: renesas: r8a779g0: Add custom clock for PLL2Geert Uytterhoeven3-7/+164
2023-01-23clk: renesas: cpg-mssr: Remove superfluous check in resume codeGeert Uytterhoeven1-3/+2
2023-01-23clk: renesas: r9a06g032: Handle h2mode setting based on USBF presenceHerve Codina1-0/+28
2023-01-12clk: renesas: cpg-mssr: Fix use after free if cpg_mssr_common_init() failedAlexey Khoroshilov1-1/+2
2023-01-12clk: renesas: r9a07g044: Add clock and reset entries for CRULad Prabhakar1-1/+25
2022-12-27clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entriesPhil Edworthy1-0/+20
2022-12-27clk: renesas: r9a09g011: Add USB clock and reset entriesBiju Das1-0/+21
2022-12-27clk: renesas: r9a09g011: Add TIM clock and reset entriesBiju Das1-0/+22
2022-12-26clk: renesas: r8a779g0: Add display related clocksTomi Valkeinen1-0/+9
2022-12-26clk: renesas: rcar-gen4: Restore PLL enum sort orderGeert Uytterhoeven1-1/+1
2022-12-26clk: renesas: r8a779g0: Fix OSC predividersGeert Uytterhoeven1-4/+4
2022-12-26clk: renesas: r9a09g011: Add PWM clock and reset entriesBiju Das1-0/+10
2022-11-16clk: renesas: r8a779f0: Fix Ethernet Switch clocksGeert Uytterhoeven1-2/+2
2022-11-15clk: renesas: r8a779g0: Add Z0 clock supportGeert Uytterhoeven1-0/+1
2022-11-08clk: renesas: r8a779g0: Add CMT clocksWolfram Sang1-0/+4
2022-11-08clk: renesas: r8a779g0: Add TMU and SASYNCRT clocksWolfram Sang1-0/+6
2022-11-08clk: renesas: r8a779f0: Fix SCIF parent clocksWolfram Sang1-4/+4
2022-11-08clk: renesas: r8a779f0: Fix HSCIF parent clocksWolfram Sang1-4/+4
2022-11-01clk: renesas: r9a06g032: Repair grave increment errorMarek Vasut1-2/+1
2022-10-28clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PMLad Prabhakar2-15/+28
2022-10-26clk: renesas: rzg2l: Fix typo in struct rzg2l_cpg_priv kerneldocLad Prabhakar1-1/+1
2022-10-26clk: renesas: r8a779a0: Fix SD0H clock nameWolfram Sang1-1/+1
2022-10-26clk: renesas: r8a779g0: Add RPC-IF clockGeert Uytterhoeven1-1/+2
2022-10-26clk: renesas: r8a779g0: Add SDHI clocksGeert Uytterhoeven1-1/+3
2022-10-26clk: renesas: r8a779f0: Add SASYNCPER internal clockGeert Uytterhoeven1-3/+5
2022-10-26clk: renesas: r8a779f0: Fix SD0H clock nameGeert Uytterhoeven1-1/+1
2022-10-26clk: renesas: r9a07g043: Drop WDT2 clock and reset entryLad Prabhakar1-5/+0
2022-10-26clk: renesas: r9a07g044: Drop WDT2 clock and reset entryLad Prabhakar1-6/+1
2022-10-26clk: renesas: r8a779g0: Add TPU clockGeert Uytterhoeven1-0/+1
2022-10-26clk: renesas: r8a779g0: Add PWM clockGeert Uytterhoeven1-0/+1
2022-10-26clk: renesas: r8a779g0: Add SCIF clocksGeert Uytterhoeven1-0/+4
2022-10-26Merge tag 'renesas-clk-fixes-for-v6.1-tag1'Geert Uytterhoeven1-4/+9
2022-10-26clk: renesas: r8a779g0: Fix HSCIF parent clocksGeert Uytterhoeven1-4/+4
2022-10-18clk: renesas: r8a779g0: Add SASYNCPER clocksGeert Uytterhoeven1-0/+5
2022-10-17clk: renesas: r9a07g044: Add MTU3a clock and reset entryBiju Das1-1/+4
2022-10-17clk: renesas: r8a779g0: Add INTC-EX clockGeert Uytterhoeven1-0/+1
2022-10-17clk: renesas: r8a779g0: Add MSIOF clocksGeert Uytterhoeven1-0/+6
2022-10-17clk: renesas: r8a779g0: Add SYS-DMAC clocksGeert Uytterhoeven1-0/+2
2022-10-17clk: renesas: r8a779f0: Add Ethernet Switch clocksYoshihiro Shimoda1-0/+2
2022-10-17clk: renesas: rzg2l: Fix typo in function nameLad Prabhakar1-3/+3
2022-10-17clk: renesas: rzg2l: Support sd clk mux round operationBiju Das1-1/+1
2022-09-18clk: renesas: r8a779g0: Add EtherAVB clocksGeert Uytterhoeven1-0/+3
2022-09-18clk: renesas: r8a779g0: Add PFC/GPIO clocksGeert Uytterhoeven1-0/+4
2022-09-18clk: renesas: r8a779g0: Add I2C clocksGeert Uytterhoeven1-0/+6
2022-09-18clk: renesas: r8a779g0: Add watchdog clockGeert Uytterhoeven1-0/+1
2022-08-29clk: renesas: r8a779f0: Add MSIOF clocksWolfram Sang1-0/+4