summaryrefslogtreecommitdiff
path: root/drivers/clk/rockchip/clk-cpu.c
AgeCommit message (Collapse)AuthorFilesLines
2022-11-14clk: rockchip: allow additional mux options for cpu-clock frequency changesElaine Zhang1-0/+41
In order to improve the main frequency of CPU, the clock path of CPU is simplified as follows: |--\ | \ |--\ --apll--|\ | \ | \ | |--apll_core--| \ | \ --24M---|/ |mux1 |--[gate]--|mux2|---clk_core | / | / --gpll--|\ | / |------| / | |--gpll_core--| / | |--/ --24M---|/ |--/ | | -------apll_directly--------------| When the CPU requests high frequency, we want to use MUX2 select the "apll_directly". At low frequencies use MUX1 to select “apll_core" and then MUX2 to select "apll_core_gate". However, in this way, the CPU frequency conversion needs to be in the following order: 1. MUX2 select to "apll_core_gate", MUX1 select "gpll_core" 2. Apll sets slow_mode, sets APLL parameters, locks APLL, and then APLL sets normal_mode 3. MUX1 select "apll_core", MUX2 select "apll_directly" So add pre_mux and post_mux options to cover this special requirements. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> [rebase] Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20221018151407.63395-7-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-11-14clk: rockchip: add register offset of the cores select parentElaine Zhang1-8/+20
The cores select parent register is special on RK3588. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20221018151407.63395-5-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-03-21clk: rockchip: support more core div settingElaine Zhang1-24/+29
Use arrays to support more core independent div settings. A55 supports each core to work at different frequencies, and each core has an independent divider control. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20210315085608.16010-4-zhangqing@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-01-26clk: rockchip: Remove unused/undocumented struct members from clk-cpuLee Jones1-4/+0
Fixes the following W=1 kernel build warning(s): drivers/clk/rockchip/clk-cpu.c:65: warning: Function parameter or member 'cpu_mux' not described in 'rockchip_cpuclk' drivers/clk/rockchip/clk-cpu.c:65: warning: Function parameter or member 'cpu_mux_ops' not described in 'rockchip_cpuclk' Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Thomas Abraham <thomas.ab@samsung.com> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210120093040.1719407-3-lee.jones@linaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner1-4/+1
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-09-28clk: rockchip: Remove superfluous error message in ↵Markus Elfring1-2/+0
rockchip_clk_register_cpuclk() Omit an extra message for a memory allocation failure in this function. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-14clk: rockchip: validity should be checked prior to cpu clock rate changeElaine Zhang1-0/+9
If validity is not checked prior to clock rate change, clk_set_rate( cpu_clk, unsupported_rate) will return success, but the real clock rate change operation is prohibited in post clock change event. Alough post clock change event will report error due to unsupported clock rate is set, but this error message is ignored by clock framework. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Tested-by: Rocky Hao <rocky.hao@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-05-30clk: rockchip: fix cpuclk registration error handlingXing Zheng1-2/+2
It maybe due to a copy-paste error the error handing should be cclk not clk when checking if the cpuclk registration succeeded. Reported-by: Lin Huang <lin.huang@rock-chips.com> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-27clk: rockchip: allow varying mux parameters for cpuclk pll-sourcesXing Zheng1-11/+18
Thers are only two parent PLLs that APLL and GPLL for core on the previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed GPLL as alternate parent when core is switching freq. Since RK3399 big.LITTLE architecture, we need to select and adapt more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-16clk: rockchip: fix coding style for clk-cpu.cShawn Lin1-1/+1
Fix the issue reported by checkpatch: ERROR: space prohibited before that ',' (ctx:WxW) + writel(clksel->val , cpuclk->reg_base + clksel->reg); Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-16clk: rockchip: disable alt_parent clk in err cases when registering cpuclkShawn Lin1-2/+4
Add clk_disable_unprepare to handle cpuclk->alt_parent if rockchip_clk_register_cpuclk fails. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-12-10clk: rockchip: allow more than 2 parents for cpuclkJeffy Chen1-2/+2
RK3228's armclk has 3 parents, so allow cpuclk to have more than 2 parents. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-07-20clk: rockchip: Properly include clk.hStephen Boyd1-0/+1
Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Only include clk.h if it's actually used. Cc: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-05clk: make several parent names constUwe Kleine-König1-1/+1
Since commit 2893c379461a ("clk: make strings in parent name arrays const") the name of parent clocks can be const. So add more const in several clock drivers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-01-17clk: rockchip: fix deadlock possibility in cpuclkHeiko Stübner1-4/+6
Lockdep reported a possible deadlock between the cpuclk lock and for example the i2c driver. CPU0 CPU1 ---- ---- lock(clk_lock); local_irq_disable(); lock(&(&i2c->lock)->rlock); lock(clk_lock); <Interrupt> lock(&(&i2c->lock)->rlock); *** DEADLOCK *** The generic clock-types of the core ccf already use spin_lock_irqsave when touching clock registers, so do the same for the cpuclk. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Michael Turquette <mturquette@linaro.org> [mturquette@linaro.org: removed initialization of "flags"]
2014-09-27clk: rockchip: add new clock-type for the cpuclkHeiko Stuebner1-0/+329
When changing the armclk on Rockchip SoCs it is supposed to be reparented to an alternate parent before changing the underlying pll and back after the change. Additionally there exist clocks that are very tightly bound to the armclk whose divider values are set according to the armclk rate. Add a special clock-type to handle all that. The rate table and divider values will be supplied from the soc-specific clock controllers. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> On a rk3288-board: Tested-by: Doug Anderson <dianders@chromium.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-10 18:38:45 +0300