summaryrefslogtreecommitdiff
path: root/drivers/clk/rockchip/clk-rk3568.c
AgeCommit message (Expand)AuthorFilesLines
2024-01-13Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds1-0/+3
2023-12-05clk: rockchip: rk3568: Mark pclk_usb as criticalChris Morgan1-0/+1
2023-12-05clk: rockchip: rk3568: Add PLL rate for 126.4MHzChris Morgan1-0/+1
2023-11-16clk: rockchip: rk3568: Add PLL rate for 292.5MHzChris Morgan1-0/+1
2023-11-16clk: rockchip: rk3568: Add PLL rate for 115.2MHzChris Morgan1-0/+1
2023-08-31Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ...Stephen Boyd1-1/+2
2023-07-19clk: Explicitly include correct DT includesRob Herring1-1/+1
2023-07-10clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHzAlibek Omarov1-1/+1
2023-07-10clk: rockchip: rk3568: Add PLL rate for 101MHzAlibek Omarov1-0/+1
2022-05-03clk: rockchip: Mark hclk_vo as critical on rk3568Sascha Hauer1-0/+1
2022-02-24clk/rockchip: Use of_device_get_match_data()Minghao Chi (CGEL ZTE)1-4/+2
2022-02-08clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference clock on rk3568Sascha Hauer1-1/+1
2022-02-08clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568Sascha Hauer1-3/+3
2022-02-08clk: rockchip: Add more PLL rates for rk3568Sascha Hauer1-0/+6
2021-11-03clk: rockchip: drop module parts from rk3399 and rk3568 driversHeiko Stuebner1-4/+0
2021-11-03Revert "clk: rockchip: use module_platform_driver_probe"Heiko Stuebner1-1/+1
2021-09-21clk: rockchip: use module_platform_driver_probeMiles Chen1-1/+1
2021-05-24clk: rockchip: fix rk3568 cpll clk gate bitsPeter Geis1-5/+5
2021-03-21clk: rockchip: add clock controller for rk3568Elaine Zhang1-0/+1725