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path: root/drivers/clk/socfpga/clk-agilex.c
AgeCommit message (Expand)AuthorFilesLines
2023-10-24clk: socfpga: agilex: Add bounds-checking coverage for struct stratix10_clock...Gustavo A. R. Silva1-6/+6
2023-08-23clk: socfpga: agilex: Convert to devm_platform_ioremap_resource()Yangtao Li1-3/+1
2023-07-19clk: Explicitly include correct DT includesRob Herring1-2/+1
2022-01-06clk: socfpga: agilex: Make use of the helper function devm_platform_ioremap_r...Cai Huoqing1-3/+1
2021-09-25clk: socfpga: agilex: fix duplicate s2f_user0_clkDinh Nguyen1-9/+0
2021-07-27clk: socfpga: agilex: add the bypass register for s2f_usr0 clockDinh Nguyen1-1/+1
2021-07-27clk: socfpga: agilex: fix up s2f_user0_clk representationDinh Nguyen1-0/+9
2021-07-27clk: socfpga: agilex: fix the parents of the psi_ref_clkDinh Nguyen1-4/+4
2021-06-28clk: agilex/stratix10: add support for the 2nd bypassDinh Nguyen1-1/+3
2021-06-28clk: agilex/stratix10: fix bypass representationDinh Nguyen1-11/+46
2021-06-28clk: agilex/stratix10: remove noc_clkDinh Nguyen1-17/+15
2021-03-31clk: socfpga: Fix code formattingStephen Boyd1-1/+2
2021-03-31clk: socfpga: Convert to s10/agilex/n5x to use clk_hwDinh Nguyen1-54/+60
2021-02-13clk: socfpga: agilex: add clock driver for eASIC N5X platformDinh Nguyen1-2/+86
2020-09-22clk: socfpga: agilex: Remove unused variable 'cntr_mux'YueHaibing1-13/+0
2020-06-20clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clkDinh Nguyen1-1/+1
2020-06-20clk: socfpga: agilex: add nand_x_clk and nand_ecc_clkDinh Nguyen1-1/+5
2020-05-27clk: socfpga: agilex: add clock driver for the Agilex platformDinh Nguyen1-0/+454