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path: root/drivers/clk/tegra/clk-pll.c
AgeCommit message (Expand)AuthorFilesLines
2021-12-15clk: tegra: Support runtime PM and power domainDmitry Osipenko1-1/+1
2021-05-31clk: tegra: Don't allow zero clock rate for PLLsDmitry Osipenko1-0/+3
2021-05-31clk: tegra: Ensure that PLLU configuration is applied properlyDmitry Osipenko1-5/+4
2021-03-24clk: tegra: Don't enable PLLE HW sequencer at initJC Kuo1-12/+0
2020-09-21clk: tegra: Always program PLL_E when enabledThierry Reding1-3/+0
2020-09-21clk: tegra: Capitalization fixesThierry Reding1-2/+2
2020-07-28clk: tegra: pll: Improve PLLM enable-state detectionDmitry Osipenko1-5/+15
2020-05-12clk: tegra: pll: Add pre/post rate-change hooksDmitry Osipenko1-1/+11
2019-11-11clk: tegra: pll: Save and restore pll contextSowjanya Komatineni1-32/+54
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner1-12/+1
2019-04-25clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides dividerDmitry Osipenko1-2/+2
2019-04-20clk: tegra: Don't enable already enabled PLLsDmitry Osipenko1-13/+37
2018-12-15clk: tegra: Return the exact clock rate from clk_round_rateRobert Yang1-3/+4
2018-03-12clk: tegra: Fix pll_u rate configurationMarcel Ziswiler1-0/+2
2017-08-24clk: tegra: Fix T210 PLLRE registrationAlex Frid1-20/+1
2017-08-24clk: tegra: Update T210 PLLSS (D2/DP) registrationAlex Frid1-39/+9
2017-08-24clk: tegra: Re-factor T210 PLLX registrationAlex Frid1-40/+0
2017-08-24clk: tegra: change post IDDQ release delay to 5usPeter De Schrijver1-1/+1
2017-08-24clk: tegra: Init cfg structure in _get_pll_mnpPeter De Schrijver1-0/+2
2017-08-24clk: tegra: Enable PLL_SS for Tegra210Peter De Schrijver1-1/+1
2017-08-24clk: tegra: fix SS control on PLL enable/disablePeter De Schrijver1-20/+24
2017-03-20clk: tegra: Rework pll_uPeter De Schrijver1-174/+0
2016-06-30clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker1-0/+505
2016-04-28clk: tegra: Fix pllre Tegra210 and add pll_re_out1Rhyland Klein1-0/+46
2016-02-02clk: tegra: Fix PLLE SS coefficientsMark Kuo1-6/+12
2016-02-02clk: tegra: Fix typos around clearing PLLE bits during enableRhyland Klein1-2/+2
2016-02-02clk: tegra: Do not disable PLLE when under hardware controlMark Kuo1-7/+15
2016-02-02clk: tegra: pll: Fix potential sleeping-while-atomicAndrew Bresticker1-3/+3
2015-12-17clk: tegra: Read correct IDDQ register in PLL_SS registrationBill Huang1-4/+7
2015-12-17clk: tegra: Fix WARN_ON in PLL_RE registrationBill Huang1-1/+2
2015-12-17clk: tegra: pll: Fix issues with rates for VCO PLLsAndrew Bresticker1-4/+12
2015-12-17clk: tegra: Add support for Tegra210 clocksRhyland Klein1-0/+5
2015-12-17clk: tegra: pll: Add logic for SSBill Huang1-1/+24
2015-12-17clk: tegra: pll: Add dyn_ramp callbackRhyland Klein1-0/+7
2015-12-17clk: tegra: pll: Add Set_default logicBill Huang1-11/+28
2015-12-17clk: tegra: pll: Adjust vco_min if SDM presentBill Huang1-0/+28
2015-12-17clk: tegra: pll: Add support for PLLMB for Tegra210Rhyland Klein1-5/+43
2015-12-17clk: tegra: pll: Add specialized logic for Tegra210Rhyland Klein1-2/+322
2015-11-20clk: tegra: pll: Update PLLM handlingDanny Huang1-49/+7
2015-11-20clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rateRhyland Klein1-41/+50
2015-11-20clk: tegra: pll: Add code to handle if resets are supported by PLLBill Huang1-0/+12
2015-11-20clk: tegra: pll: Add logic for out-of-table rates for T210Rhyland Klein1-2/+22
2015-11-20clk: tegra: pll: Add logic for handling SDM dataRhyland Klein1-1/+65
2015-11-20clk: tegra: pll: Don't unconditionally set LOCK flagsRhyland Klein1-9/+2
2015-11-20clk: tegra: pll: Update warning messageRhyland Klein1-1/+2
2015-11-20clk: tegra: pll: Simplify clk_enable_pathRhyland Klein1-54/+22
2015-11-20clk: tegra: pll: Add tegra_pll_wait_for_lock to clk headerRhyland Klein1-0/+5
2015-11-20clk: tegra: Constify pdiv-to-hw mappingsThierry Reding1-3/+3
2015-11-18clk: tegra: Miscellaneous coding style cleanupsThierry Reding1-3/+3
2015-08-25clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)Stephen Boyd1-4/+4