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path: root/drivers/clk/tegra
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2022-03-12clk: tegra: tegra124-emc: Fix missing put_device() call in emc_ensure_emc_driverMiaoqian Lin1-0/+1
2021-12-15clk: tegra: Support runtime PM and power domainDmitry Osipenko8-54/+420
2021-12-15clk: tegra: Make vde a child of pll_p on tegra114Dmitry Osipenko1-1/+1
2021-09-03Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2-6/+2
2021-08-29clk: tegra: fix old-style declarationArnd Bergmann1-1/+1
2021-08-11clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clockDmitry Osipenko1-5/+1
2021-07-28clk: tegra: Implement disable_unused() of tegra_clk_sdmmc_mux_opsDmitry Osipenko1-0/+10
2021-06-26clk: tegra: clk-tegra124-dfll-fcpu: don't use devm functions for regulatorAlexandru Ardelean1-2/+2
2021-06-02clk: tegra: tegra124-emc: Fix clock imbalance in emc_set_timing()Yang Yingliang1-1/+3
2021-05-31clk: tegra: Don't deassert reset on enabling clocksDmitry Osipenko3-13/+1
2021-05-31clk: tegra: Mark external clocks as not having reset controlDmitry Osipenko1-3/+3
2021-05-31clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttlingDmitry Osipenko2-3/+15
2021-05-31clk: tegra: Don't allow zero clock rate for PLLsDmitry Osipenko1-0/+3
2021-05-31clk: tegra: Halve SCLK rate on Tegra20Dmitry Osipenko1-3/+3
2021-05-31clk: tegra: Ensure that PLLU configuration is applied properlyDmitry Osipenko1-5/+4
2021-05-31clk: tegra: Fix refcounting of gate clocksDmitry Osipenko2-25/+58
2021-05-31clk: tegra30: Use 300MHz for video decoder by defaultDmitry Osipenko1-1/+1
2021-03-24clk: tegra: Don't enable PLLE HW sequencer at initJC Kuo1-12/+0
2021-03-24clk: tegra: Add PLLE HW power sequencer controlJC Kuo1-1/+52
2021-02-22Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2-4/+2
2021-02-21Merge tag 'arm-drivers-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/gi...Linus Torvalds5-15/+75
2021-02-11clk: tegra: cvb: Provide missing description for 'tegra_cvb_add_opp_table()'s...Lee Jones1-0/+1
2021-02-11clk: tegra: clk-tegra30: Remove unused variable 'reg'Lee Jones1-4/+1
2021-01-12clk: tegra30: Add hda clock default rates to clock driverPeter Geis1-0/+2
2021-01-05memory: tegra124-emc: Make driver modularDmitry Osipenko5-15/+75
2020-12-21Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds4-6/+7
2020-12-10clk: tegra: Fix duplicated SE clock entryDmitry Osipenko2-1/+2
2020-11-26clk: tegra: bpmp: Clamp clock rates on requestsSivaram Nair1-3/+3
2020-11-20clk: tegra: Do not return 0 on failureNicolin Chen1-2/+2
2020-11-06clk: tegra: Export Tegra20 EMC kernel symbolsDmitry Osipenko1-0/+3
2020-10-22Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds1-1/+1
2020-09-24clk: tegra: Drop !provider check in tegra210_clk_emc_set_rate()Stephen Boyd1-1/+1
2020-09-21clk: tegra: Fix missing prototype for tegra210_clk_register_emc()Thierry Reding1-0/+2
2020-09-21clk: tegra: Always program PLL_E when enabledThierry Reding1-3/+0
2020-09-21clk: tegra: Capitalization fixesThierry Reding1-2/+2
2020-07-28clk: tegra: pll: Improve PLLM enable-state detectionDmitry Osipenko1-5/+15
2020-06-10Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds10-32/+700
2020-05-13clk: tegra: Fix initial rate for pll_a on Tegra124Thierry Reding1-1/+1
2020-05-12clk: tegra: Add Tegra210 CSI TPG clock gateSowjanya Komatineni1-0/+7
2020-05-12clk: tegra30: Use custom CCLK implementationDmitry Osipenko1-2/+4
2020-05-12clk: tegra20: Use custom CCLK implementationDmitry Osipenko1-2/+5
2020-05-12clk: tegra: cclk: Add helpers for handling PLLX rate changesDmitry Osipenko2-0/+36
2020-05-12clk: tegra: pll: Add pre/post rate-change hooksDmitry Osipenko2-1/+17
2020-05-12clk: tegra: Add custom CCLK implementationDmitry Osipenko3-2/+188
2020-05-12clk: tegra: Remove the old emc_mux clock for Tegra210Joseph Lo1-19/+31
2020-05-12clk: tegra: Implement Tegra210 EMC clockJoseph Lo3-0/+373
2020-05-12clk: tegra: Export functions for EMC clock scalingJoseph Lo1-0/+26
2020-05-12clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210Joseph Lo1-0/+11
2020-05-12clk: tegra: Rename Tegra124 EMC clock source fileThierry Reding4-6/+2
2020-03-25clk: tegra: Use NULL for pointer initializationStephen Boyd1-1/+1