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path: root/drivers/clk/x86
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2022-10-27clk: mxl: syscon_node_to_regmap() returns error pointersRahul Tanwar1-1/+1
2022-10-18clk: mxl: Fix a clk entry by adding relevant flagsRahul Tanwar3-4/+6
2022-10-18clk: mxl: Add option to override gate clksRahul Tanwar2-1/+16
2022-10-18clk: mxl: Remove redundant spinlocksRahul Tanwar4-91/+9
2022-10-18clk: mxl: Switch from direct readl/writel based IO to regmap based IORahul Tanwar5-29/+42
2022-06-12platform/x86: Drop the PMC_ATOM Kconfig optionHans de Goede1-3/+1
2022-01-07clk: x86: Fix clk_gate_flags for RV_CLK_GATEAjit Kumar Pandey1-1/+1
2022-01-07clk: x86: Use dynamic con_id string during clk registrationAjit Kumar Pandey1-2/+2
2022-01-07x86: clk: clk-fch: Add support for newer family of AMD's SOCAjit Kumar Pandey1-11/+31
2021-07-28clk: x86: Rename clk-lpt to more specific clk-lpss-atomAndy Shevchenko2-7/+7
2020-08-15Merge tag 'acpi-5.9-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/r...Linus Torvalds3-79/+102
2020-08-07clk: x86: Support RV architectureAkshu Agrawal1-15/+38
2020-08-07clk: x86: Change name from ST to FCHAkshu Agrawal2-13/+13
2020-08-07ACPI: APD: Change name from ST to FCHAkshu Agrawal1-2/+2
2020-07-24clk: intel: Avoid unnecessary memset by improving codeRahul Tanwar1-4/+3
2020-07-24clk: intel: Improve locking in the driverRahul Tanwar1-12/+5
2020-07-24clk: intel: Use devm_clk_hw_register() instead of clk_hw_register()Rahul Tanwar2-5/+5
2020-05-29clk: intel: remove redundant initialization of variable rate64Colin Ian King1-1/+1
2020-05-27clk: intel: Add CGU clock driver for a new SoCRahul Tanwar6-0/+1611
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner1-4/+1
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288Thomas Gleixner1-9/+1
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner1-0/+1
2019-05-15clk: Remove io.h from clk-provider.hStephen Boyd1-0/+1
2019-04-11clk: x86: Add system specific quirk to mark clocks as criticalDavid Müller1-3/+11
2019-03-08Merge branches 'clk-qcom-msm8998', 'clk-fractional-parent', 'clk-x86-mv' and ...Stephen Boyd1-1/+1
2019-02-22clk: x86: Move clk-lpss.h to platform_data/x86Andy Shevchenko1-1/+1
2019-02-06clk: clk-st: avoid clkdev lookup leak at removeMatti Vaittinen1-1/+2
2018-09-18clk: x86: Stop marking clocks as CLK_IS_CRITICALHans de Goede1-7/+0
2018-09-18clk: x86: add "ether_clk" alias for Bay Trail / Cherry TrailHans de Goede1-0/+11
2018-08-31clk: x86: Set default parent to 48MhzAkshu Agrawal1-1/+1
2018-05-17clk: x86: Add ST oscout platform clockAkshu Agrawal2-1/+79
2017-07-19clk: x86: Do not gate clocks enabled by the firmwareCarlo Caione1-0/+7
2017-05-01clk: x86: pmc-atom: Checking for IS_ERR() instead of NULLDan Carpenter1-2/+2
2017-04-19clk: x86: add "mclk" alias for Baytrail/CherrytrailPierre-Louis Bossart1-0/+7
2017-01-27clk: x86: Add Atom PMC platform clocksIrina Tirdea2-0/+372
2016-03-03clk: x86: Remove clkdev.h and clk.h includesStephen Boyd1-2/+0
2016-03-03clk: x86: Remove CLK_IS_ROOTStephen Boyd1-1/+1
2014-10-20clk: x86: drop owner assignment from platform_driversWolfram Sang1-1/+0
2013-06-19ACPI / LPSS: add support for Intel BayTrailMika Westerberg1-3/+1
2013-05-14ACPI / LPSS: register clock device for Lynxpoint DMA properlyRafael J. Wysocki1-4/+11
2013-03-22ACPI / scan: Add special handler for Intel Lynxpoint LPSS devicesRafael J. Wysocki4-175/+2
2013-01-24clk: x86: add support for Lynxpoint LPSS clocksMika Westerberg4-0/+223