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path: root/drivers/clk/zte
AgeCommit message (Expand)AuthorFilesLines
2017-04-12clk: zte: Mark pll config tables as constStephen Boyd1-2/+2
2017-04-12clk: zte: add pll_vga clock for zx296718Shawn Guo1-0/+24
2017-04-12clk: zte: pd_bit is not 0 on zx296718Shawn Guo2-2/+16
2017-04-12clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocksShawn Guo1-3/+3
2017-02-10clk: zte: add i2s clocks for zx296718Baoyou Xie1-0/+4
2017-01-10clk: zte: add audio clocks for zx296718Jun Nie3-0/+275
2017-01-10clk: zx296718: do not panic on failureShawn Guo1-9/+18
2016-09-24clk: zx296718: register driver earlier with core_initcallShawn Guo1-1/+5
2016-09-17clk: zx: fix pointer case warningsArnd Bergmann1-10/+10
2016-09-17clk: zx296718: use builtin_platform_driver to simplify the codeWei Yongjun1-5/+1
2016-09-14clk: zx: register ZX296718 clocksJun Nie3-0/+1050
2016-09-14clk: zx: reform pll config info to ease code extensionJun Nie2-9/+16
2016-04-16clk: zte: Remove CLK_IS_ROOTStephen Boyd1-2/+1
2015-07-28clk: zx: Constify parent names in clock init dataJun Nie1-20/+20
2015-07-28clk: zx: Add audio and GPIO clock for zx296702Jun Nie1-2/+90
2015-07-28clk: zx: Add audio div clock method for zx296702Jun Nie3-3/+149
2015-06-12clk: zx: add clock support to zx296702Jun Nie4-0/+863