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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2019-05-15clk: Remove io.h from clk-provider.hStephen Boyd124-6/+130
2019-05-07Merge branch 'clk-parent-rewrite-1' into clk-nextStephen Boyd4-113/+322
2019-05-07Merge branch 'clk-ti' into clk-nextStephen Boyd15-18/+40
2019-05-07Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and...Stephen Boyd52-229/+2265
2019-05-07Merge branches 'clk-hisi', 'clk-lochnagar', 'clk-allwinner', 'clk-rockchip' a...Stephen Boyd17-66/+576
2019-05-07Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-...Stephen Boyd12-90/+178
2019-05-07Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and 'clk-basic-be'...Stephen Boyd29-626/+2363
2019-05-07Merge branches 'clk-renesas', 'clk-qcom', 'clk-mtk', 'clk-milbeaut' and 'clk-...Stephen Boyd52-203/+4615
2019-05-03clk: Cache core in clk_fetch_parent_index() without namesStephen Boyd1-10/+27
2019-05-03clk: imx: correct pfdv2 gate_bit/vld_bit operationsAnson Huang1-5/+5
2019-05-03clk: sifive: add a driver for the SiFive FU540 PRCI IP blockPaul Walmsley5-0/+647
2019-05-03clk: analogbits: add Wide-Range PLL libraryPaul Walmsley5-0/+372
2019-05-03clk: imx: clk-pllv3: mark expected switch fall-throughsGustavo A. R. Silva1-0/+2
2019-05-02clk: imx8mq: Add dsi_ipg_divGuido Günther1-0/+1
2019-05-02clk: imx: pllv4: add fractional-N pll supportAnson Huang1-9/+63
2019-05-01clk: sunxi-ng: Use the correct style for SPDX License IdentifierNishad Kamdar2-3/+3
2019-05-01clk: sprd: Use the correct style for SPDX License IdentifierNishad Kamdar6-6/+6
2019-05-01clk: renesas: Use the correct style for SPDX License IdentifierNishad Kamdar3-6/+6
2019-05-01clk: qcom: Use the correct style for SPDX License IdentifierNishad Kamdar1-1/+1
2019-05-01clk: davinci: Use the correct style for SPDX License IdentifierNishad Kamdar2-2/+2
2019-05-01clk: actions: Use the correct style for SPDX License IdentifierNishad Kamdar9-9/+9
2019-04-30clk: imx: keep uart clock on during system bootJacky Bai1-0/+16
2019-04-30clk: imx: correct i.MX7D AV PLL num/denom offsetAnson Huang3-10/+24
2019-04-29clk: stm32mp1: Add ddrperfm clockGabriel Fernandez1-0/+3
2019-04-26clk: Remove CLK_IS_BASIC clk flagStephen Boyd11-11/+10
2019-04-26clock: milbeaut: Add Milbeaut M10V clock controllerSugaya Taichi2-0/+664
2019-04-26clk: imx6sll: Fix mispelling uart4_serial as serailLeonard Crestez1-1/+1
2019-04-26clk: imx: pll14xx: drop unused variablePeng Fan1-4/+2
2019-04-26clk: mediatek: add clock driver for MT8516Fabien Parent3-0/+824
2019-04-26clk: at91: Mark struct clk_range as constStephen Boyd7-14/+14
2019-04-26clk: at91: add sam9x60 pmc driverAlexandre Belloni2-0/+308
2019-04-25clk: tegra: divider: Mark Memory Controller clock as read-onlyDmitry Osipenko1-1/+2
2019-04-25clk: tegra: emc: Replace BUG() with WARN_ONCE()Dmitry Osipenko1-1/+4
2019-04-25clk: tegra: emc: Fix EMC max-rate clampingDmitry Osipenko1-7/+10
2019-04-25clk: tegra: emc: Support multiple RAM codesDmitry Osipenko1-14/+23
2019-04-25clk: tegra: emc: Don't enable EMC clock manuallyDmitry Osipenko1-2/+0
2019-04-25clk: at91: add sam9x60 PLL driverAlexandre Belloni3-0/+337
2019-04-25clk: at91: master: Add sam9x60 supportAlexandre Belloni2-3/+6
2019-04-25clk: at91: usb: Add sam9x60 supportAlexandre Belloni2-6/+30
2019-04-25clk: at91: allow configuring generated PCR layoutAlexandre Belloni4-24/+29
2019-04-25clk: at91: allow configuring peripheral PCR layoutAlexandre Belloni6-22/+71
2019-04-25clk: stm32: Introduce clocks of STM32F769 boardGabriel Fernandez1-8/+299
2019-04-25clk: at91: sckc: handle different RC startup timeAlexandre Belloni1-2/+15
2019-04-25clk: at91: modernize sckc bindingAlexandre Belloni1-89/+36
2019-04-25clk: qoriq: increase array size of cmux_to_groupYogesh Gaur1-2/+2
2019-04-25clk: qoriq: Add ls1028a clock configurationYuantian Tang1-0/+68
2019-04-25clk: qoriq: add more PLL divider clocks supportYuantian Tang1-2/+3
2019-04-25clk: ti: dra7: disable the RNG and TIMER12 clkctrl clocks on HS devicesTero Kristo4-8/+12
2019-04-25clk: ti: dra7x: prevent non-existing clkctrl clocks from registeringTero Kristo4-2/+22
2019-04-25clk: ti: export the omap2_clk_is_hw_omap callTero Kristo1-1/+0