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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2019-01-26clk: imx6q: reset exclusive gates on initLucas Stach1-1/+5
2019-01-26clk: imx: make mux parent strings constA.s. Dong3-9/+13
2019-01-09clk: rockchip: fix typo in rk3188 spdif_frac parentJohan Jonker1-1/+1
2018-12-21clk: mmp: Off by one in mmp_clk_add()Dan Carpenter1-1/+1
2018-12-21clk: mvebu: Off by one bugs in cp110_of_clk_get()Dan Carpenter1-2/+2
2018-12-01clk: samsung: exynos5250: Add missing clocks for FIMC LITE SYSMMU devicesMarek Szyprowski1-0/+6
2018-11-27clk: fixed-factor: fix of_node_get-put imbalanceRicardo Ribalda Delgado1-0/+1
2018-11-27clk: samsung: exynos5420: Enable PERIS clocks for suspendMarek Szyprowski1-0/+1
2018-11-27clk: fixed-rate: fix of_node_get-put imbalanceAlan Tull1-0/+1
2018-11-21reset: hisilicon: fix potential NULL pointer dereferenceGustavo A. R. Silva1-3/+2
2018-11-21clk: mvebu: use correct bit for 98DX3236 NANDChris Packham1-1/+1
2018-11-21clk: rockchip: Fix static checker warning in rockchip_ddrclk_get_parent callEnric Balletbo i Serra1-4/+0
2018-11-21clk: at91: Fix division by zero in PLL recalc_rate()Ronald Wahl1-0/+3
2018-11-21clk: s2mps11: Fix matching when built as module and DT node contains compatibleKrzysztof Kozlowski1-0/+30
2018-10-18clk: x86: Stop marking clocks as CLK_IS_CRITICALHans de Goede1-7/+0
2018-10-18clk: x86: add "ether_clk" alias for Bay Trail / Cherry TrailHans de Goede1-0/+11
2018-09-26clk: tegra: bpmp: Don't crash when a clock fails to registerMikko Perttunen1-3/+9
2018-09-26clk: clk-fixed-factor: Clear OF_POPULATED flag in case of failureRajan Vaja1-1/+8
2018-09-26clk: core: Potentially free connection idMikko Perttunen1-0/+3
2018-09-26clk: imx6ul: fix missing of_node_put()Nicholas Mc Guire1-0/+1
2018-09-15clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399Levin Du1-0/+1
2018-09-05clk: rockchip: fix clk_i2sout parent selection bits on rk3399Alberto Panizzo1-1/+1
2018-08-17clk: sunxi-ng: Fix missing CLK_SET_RATE_PARENT in ccu-sun4i-a10.cAlexander Syring1-1/+1
2018-07-03clk: at91: PLL recalc_rate() now using cached MUL and DIV valuesMarcin Ziemianowicz1-12/+1
2018-07-03clk: renesas: cpg-mssr: Stop using printk format %pCrGeert Uytterhoeven1-4/+5
2018-06-20clk: imx6ull: use OSC clock during AXI rate changeStefan Agner1-1/+1
2018-06-20clk: honor CLK_MUX_ROUND_CLOSEST in generic clk muxJerome Brunet2-4/+13
2018-05-25clk: samsung: exynos3250: Fix PLL ratesAndrzej Hajda1-2/+2
2018-05-25clk: samsung: exynos5250: Fix PLL ratesAndrzej Hajda1-4/+4
2018-05-25clk: samsung: exynos5433: Fix PLL ratesAndrzej Hajda1-6/+6
2018-05-25clk: samsung: exynos5260: Fix PLL ratesAndrzej Hajda1-1/+1
2018-05-25clk: samsung: exynos7: Fix PLL ratesAndrzej Hajda1-1/+1
2018-05-25clk: samsung: s3c2410: Fix PLL ratesAndrzej Hajda1-8/+8
2018-05-25clk: rockchip: Prevent calculating mmc phase if clock rate is zeroShawn Lin1-0/+23
2018-05-25clk: tegra: Fix pll_u rate configurationMarcel Ziswiler1-0/+2
2018-05-25clk: hisilicon: mark wdt_mux_p[] as constArnd Bergmann1-1/+1
2018-05-25clk: Don't show the incorrect clock phaseShawn Lin1-0/+3
2018-05-25clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228Shawn Lin1-1/+1
2018-04-24clk: bcm2835: De-assert/assert PLL reset signal when appropriateBoris Brezillon1-3/+5
2018-04-24clk: mediatek: fix PWM clock source by adding a fixed-factor clockSean Wang1-7/+8
2018-04-24clk: fix false-positive Wmaybe-uninitialized warningArnd Bergmann1-3/+3
2018-04-24clk: mvebu: armada-38x: add support for missing clocksRichard Genoud1-7/+7
2018-04-12clk: sunxi-ng: a83t: Add M divider to TCON1 clockJernej Škrabec1-2/+2
2018-04-12clk: divider: fix incorrect usage of container_ofJerome Brunet5-8/+7
2018-04-12clk: meson: mpll: use 64-bit maths in params_from_rateMartin Blumenstingl1-1/+1
2018-03-28clk: sunxi-ng: a31: Fix CLK_OUT_* clock opsChen-Yu Tsai1-3/+3
2018-03-28clk: bcm2835: Protect sections updating shared registersBoris Brezillon1-0/+4
2018-03-28clk: bcm2835: Fix ana->maskX definitionsBoris Brezillon1-4/+4
2018-03-24clk: migrate the count of orphaned clocks at initJerome Brunet1-16/+21
2018-03-24clk: si5351: Rename internal plls to avoid name collisionsSergej Sawazki1-1/+1