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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2018-04-24clk: bcm2835: De-assert/assert PLL reset signal when appropriateBoris Brezillon1-3/+5
2018-04-24clk: mediatek: fix PWM clock source by adding a fixed-factor clockSean Wang1-7/+8
2018-04-24clk: fix false-positive Wmaybe-uninitialized warningArnd Bergmann1-3/+3
2018-04-24clk: mvebu: armada-38x: add support for missing clocksRichard Genoud1-7/+7
2018-04-12clk: sunxi-ng: a83t: Add M divider to TCON1 clockJernej Škrabec1-2/+2
2018-04-12clk: divider: fix incorrect usage of container_ofJerome Brunet5-8/+7
2018-04-12clk: meson: mpll: use 64-bit maths in params_from_rateMartin Blumenstingl1-1/+1
2018-03-28clk: sunxi-ng: a31: Fix CLK_OUT_* clock opsChen-Yu Tsai1-3/+3
2018-03-28clk: bcm2835: Protect sections updating shared registersBoris Brezillon1-0/+4
2018-03-28clk: bcm2835: Fix ana->maskX definitionsBoris Brezillon1-4/+4
2018-03-24clk: migrate the count of orphaned clocks at initJerome Brunet1-16/+21
2018-03-24clk: si5351: Rename internal plls to avoid name collisionsSergej Sawazki1-1/+1
2018-03-24clk: axi-clkgen: Correctly handle nocount bit in recalc_rate()Lars-Peter Clausen1-5/+24
2018-03-24clk: Don't touch hardware when reparenting during registrationStephen Boyd1-2/+5
2018-03-24clk: at91: pmc: Wait for clocks when resumingRomain Izard1-8/+16
2018-03-19clk: qcom: msm8916: fix mnd_width for codec_digcodecSrinivas Kandagatla1-0/+1
2018-03-19clk: meson: gxbb: fix wrong clock for SARADC/SANAYixun Lan1-2/+2
2017-12-29clk: sunxi: sun9i-mmc: Implement reset callback for reset controlsChen-Yu Tsai1-0/+12
2017-12-25clk: sunxi-ng: sun6i: Rename HDMI DDC clock to avoid name collisionChen-Yu Tsai1-1/+1
2017-12-25clk: sunxi-ng: sun5i: Fix bit offset of audio PLL post-dividerChen-Yu Tsai1-2/+2
2017-12-25clk: sunxi-ng: nm: Check if requested rate is supported by fractional clockChen-Yu Tsai1-0/+3
2017-12-20clk: tegra: Fix cclk_lp divisor registerMichał Mirosław1-1/+1
2017-12-20clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()Nicolin Chen1-2/+2
2017-12-20clk: hi6220: mark clock cs_atb_syspll as criticalLeo Yan1-1/+1
2017-12-20clk: imx6: refine hdmi_isfr's parent to make HDMI work on i.MX6 SoCs w/o VPUSébastien Szymanski1-1/+1
2017-12-20clk: imx: imx7d: Fix parent clock for OCRAM_CLKAdriana Reus1-1/+1
2017-12-20clk: mediatek: add the option for determining PLL source clockChen Zhong2-1/+5
2017-12-14clk: hi3660: fix incorrect uart3 clock freqencyZhong Kaihua1-1/+1
2017-12-14clk: uniphier: fix DAPLL2 clock rate of Pro5Masahiro Yamada1-1/+1
2017-12-14clk: qcom: common: fix legacy board-clock registrationJohan Hovold1-2/+4
2017-12-14clk: sunxi-ng: a83t: Fix i2c buses bitsMylene JOSSERAND1-2/+2
2017-12-14clk: stm32h7: fix test of clock configGabriel Fernandez1-2/+2
2017-11-30clk: ti: dra7-atl-clock: fix child-node lookupsJohan Hovold1-2/+1
2017-11-03Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds1-3/+3
2017-11-03Update MIPS email addressesPaul Burton5-5/+5
2017-11-02License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman45-0/+45
2017-10-24clk: uniphier: fix clock data for PXs3Masahiro Yamada1-3/+3
2017-10-04clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycleMarek Szyprowski1-0/+15
2017-09-30Merge tag 'v4.14-rockchip-clkfixes-1' of git://git.kernel.org/pub/scm/linux/k...Stephen Boyd1-5/+7
2017-09-30clk: Export clk_bulk_prepare()Bjorn Andersson1-0/+1
2017-09-17clk: rockchip: add sclk_timer5 as critical clock on rk3128Elaine Zhang1-0/+1
2017-09-17clk: rockchip: fix up rk3128 pvtm and mipi_24m gate regs errorElaine Zhang1-4/+4
2017-09-17clk: rockchip: add pclk_pmu as critical clock on rk3128Elaine Zhang1-1/+2
2017-09-13Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds114-1037/+8040
2017-09-11Merge tag 'armsoc-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/gi...Linus Torvalds4-210/+21
2017-09-02clk: si5351: fix PLL resetRussell King1-7/+5
2017-09-02clk: at91: clk-generated: make gclk determine audio_pll rateQuentin Schulz1-6/+57
2017-09-02clk: at91: clk-generated: create function to find best_diffQuentin Schulz1-14/+27
2017-09-02clk: at91: add audio pll clock driversQuentin Schulz2-0/+537
2017-09-02clk: at91: clk-generated: remove useless divisor loopQuentin Schulz1-13/+12