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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2020-02-05clk: mmp2: Fix the order of timer mux parentsLubomir Rintel1-1/+1
2020-01-29clk: armada-xp: fix refcount leak in axp_clk_init()Yangtao Li1-1/+3
2020-01-29clk: kirkwood: fix refcount leak in kirkwood_clk_init()Yangtao Li1-0/+2
2020-01-29clk: armada-370: fix refcount leak in a370_clk_init()Yangtao Li1-1/+3
2020-01-29clk: vf610: fix refcount leak in vf610_clocks_init()Yangtao Li1-0/+1
2020-01-29clk: imx7d: fix refcount leak in imx7d_clocks_init()Yangtao Li1-0/+1
2020-01-29clk: imx6sx: fix refcount leak in imx6sx_clocks_init()Yangtao Li1-0/+1
2020-01-29clk: imx6q: fix refcount leak in imx6q_clocks_init()Yangtao Li1-0/+1
2020-01-29clk: samsung: exynos4: fix refcount leak in exynos4_get_xom()Yangtao Li1-0/+1
2020-01-29clk: socfpga: fix refcount leakYangtao Li2-0/+2
2020-01-29clk: qoriq: fix refcount leak in clockgen_init()Yangtao Li1-0/+1
2020-01-29clk: highbank: fix refcount leak in hb_clk_init()Yangtao Li1-0/+1
2020-01-23clk: samsung: exynos5420: Preserve CPU clocks configuration during suspend/re...Marian Mihailescu1-0/+2
2020-01-04clk: pxa: fix one of the pxa RTC clocksRobert Jarzmik1-0/+1
2020-01-04clk: qcom: Allow constant ratio freq tables for rcgJeffrey Hugo2-0/+5
2019-12-21clk: rockchip: fix rk3188 sclk_mac_lbtest parameter orderingHeiko Stuebner1-2/+2
2019-12-21clk: rockchip: fix rk3188 sclk_smc gate dataFinley Xiao1-2/+2
2019-12-05clk: samsung: exynos5420: Preserve PLL configuration during suspend/resumeMarek Szyprowski1-0/+6
2019-11-28clk: mmp2: fix the clock id for sdh2_clk and sdh3_clkLubomir Rintel1-2/+2
2019-10-07clk: sirf: Don't reference clk_init_data after registrationStephen Boyd1-4/+8
2019-10-07clk: qoriq: Fix -Wunused-const-variableNathan Huckleberry1-1/+1
2019-09-21clk: rockchip: Don't yell about bad mmc phases when gettingDouglas Anderson1-3/+1
2019-09-16clk: s2mps11: Add used attribute to s2mps11_dt_matchNathan Chancellor1-1/+1
2019-06-22clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288Douglas Anderson1-0/+11
2019-06-11clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides dividerDmitry Osipenko1-2/+2
2019-03-23clk: ingenic: Fix round_rate misbehaving with non-integer dividersPaul Cercueil1-5/+5
2019-02-20clk: imx6sl: ensure MMDC CH0 handshake is bypassedAnson Huang1-0/+6
2019-01-26clk: imx6q: reset exclusive gates on initLucas Stach1-1/+5
2018-12-21clk: mmp: Off by one in mmp_clk_add()Dan Carpenter1-1/+1
2018-11-27clk: samsung: exynos5420: Enable PERIS clocks for suspendMarek Szyprowski1-0/+1
2018-11-21clk: s2mps11: Fix matching when built as module and DT node contains compatibleKrzysztof Kozlowski1-0/+30
2018-09-26clk: imx6ul: fix missing of_node_put()Nicholas Mc Guire1-0/+1
2018-07-25clk: tegra: Fix PLL_U post divider and initial rate on Tegra30Lucas Stach1-5/+6
2018-05-30clk: samsung: exynos3250: Fix PLL ratesAndrzej Hajda1-2/+2
2018-05-30clk: samsung: exynos5250: Fix PLL ratesAndrzej Hajda1-4/+4
2018-05-30clk: samsung: exynos5433: Fix PLL ratesAndrzej Hajda1-6/+6
2018-05-30clk: samsung: exynos5260: Fix PLL ratesAndrzej Hajda1-1/+1
2018-05-30clk: samsung: s3c2410: Fix PLL ratesAndrzej Hajda1-8/+8
2018-05-30clk: rockchip: Prevent calculating mmc phase if clock rate is zeroShawn Lin1-0/+23
2018-05-30clk: Don't show the incorrect clock phaseShawn Lin1-0/+3
2018-04-24clk: bcm2835: De-assert/assert PLL reset signal when appropriateBoris Brezillon1-3/+5
2018-04-24clk: mvebu: armada-38x: add support for missing clocksRichard Genoud1-7/+7
2018-04-24clk: mvebu: armada-38x: add support for 1866MHz variantsRalph Sennhauser1-3/+4
2018-04-13clk: Fix __set_clk_rates error print-stringBryan O'Donoghue1-1/+1
2018-04-13clk: scpi: fix return type of __scpi_dvfs_round_rateSudeep Holla1-3/+3
2018-03-28clk: bcm2835: Protect sections updating shared registersBoris Brezillon1-0/+4
2018-03-24clk: si5351: Rename internal plls to avoid name collisionsSergej Sawazki1-1/+1
2018-03-24clk: ns2: Correct SDIO bitsBharat Kumar Reddy Gooty1-1/+1
2018-03-22clk: qcom: msm8916: fix mnd_width for codec_digcodecSrinivas Kandagatla1-0/+1
2017-12-20clk: tegra: Fix cclk_lp divisor registerMichał Mirosław1-1/+1