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path: root/drivers/clk
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2014-01-20Merge branch 'drm-intel-next' of git://people.freedesktop.org/~danvet/drm-int...Dave Airlie5-15/+19
2014-01-08clk: clk-divider: fix divisor > 255 bugJames Hogan1-1/+1
2014-01-06Merge tag 'samsung-clk-fixes' of git://git.kernel.org/pub/scm/linux/kernel/gi...Mike Turquette3-11/+15
2013-12-30clk: exynos: File scope reg_save array should depend on PM_SLEEPKrzysztof Kozlowski1-5/+5
2013-12-30clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clockAbhilash Kesavan1-1/+2
2013-12-30clk: samsung: exynos5250: Add MDMA0 clocksAbhilash Kesavan1-1/+4
2013-12-30clk: samsung: exynos5250: Fix ACP gate register offsetAbhilash Kesavan1-1/+1
2013-12-30clk: exynos5250: fix sysmmu_mfc{l,r} gate clocksAndrew Bresticker1-2/+2
2013-12-30clk: samsung: exynos4: Correct SRC_MFC registerSeung-Woo Kim1-1/+1
2013-12-16mfd: s2mps11: Fix build after regmap field rename in sec-core.cKrzysztof Kozlowski1-3/+3
2013-12-12clk: tegra: remove bogus PCIE_XCLKStephen Warren2-13/+0
2013-12-12clk: tegra: remove legacy reset APIsStephen Warren3-63/+0
2013-12-12clk: tegra: implement a reset driverStephen Warren6-6/+57
2013-11-28clk: tegra: fix __clk_lookup() return value checksWei Yongjun1-4/+4
2013-11-28clk: tegra: Do not print errors for clk_round_rate()Thierry Reding1-6/+3
2013-11-26clk: tegra: Initialize DSI low-power clocksThierry Reding1-0/+2
2013-11-26clk: tegra: add FUSE clock deviceAlexandre Courbot4-1/+4
2013-11-26clk: tegra: Properly setup PWM clock on Tegra30Thierry Reding1-1/+3
2013-11-26clk: tegra: Initialize secondary gr3d clock on Tegra30Thierry Reding1-0/+1
2013-11-26clk: tegra114: Initialize clocks needed for HDMIMikko Perttunen1-0/+2
2013-11-26clk: tegra124: add suspend/resume function for tegra_cpu_car_opsJoseph Lo1-0/+27
2013-11-26clk: tegra124: add wait_for_reset and disable_clock for tegra_cpu_car_opsJoseph Lo1-0/+26
2013-11-26clk: tegra124: Add support for Tegra124 clocksPeter De Schrijver2-0/+1371
2013-11-26clk: tegra124: Add new peripheral clocksPeter De Schrijver1-0/+69
2013-11-26clk: tegra124: Add common clk IDs to clk-id.hPeter De Schrijver1-0/+22
2013-11-26clk: tegra: add TEGRA_PERIPH_NO_GATEPeter De Schrijver3-3/+22
2013-11-26clk: tegra: add locking to periph clksPeter De Schrijver2-19/+24
2013-11-26clk: tegra: Add periph regs bank XPeter De Schrijver1-0/+10
2013-11-26clk: tegra: Add support for PLLSSPeter De Schrijver2-2/+126
2013-11-26clk: tegra: move tegra20 to common infraPeter De Schrijver1-402/+255
2013-11-26clk: tegra: move tegra30 to common infraPeter De Schrijver1-895/+403
2013-11-26clk: tegra: introduce common gen4 super clockPeter De Schrijver4-74/+155
2013-11-26clk: tegra: move PMC, fixed clocks to common filesPeter De Schrijver5-74/+253
2013-11-26clk: tegra: move periph clocks to common filePeter De Schrijver6-581/+627
2013-11-26clk: tegra: move audio clk to common filePeter De Schrijver4-208/+402
2013-11-26clk: tegra: add clkdev registration infraPeter De Schrijver3-159/+179
2013-11-26clk: tegra: add common infra for DT clocksPeter De Schrijver2-0/+16
2013-11-26clk: tegra: add header for common tegra clock IDsPeter De Schrijver1-0/+213
2013-11-26clk: tegra: move fields to tegra_clk_pll_paramsPeter De Schrijver5-177/+175
2013-11-26clk: tegra: use pll_ref as the pll_e parentPeter De Schrijver2-4/+7
2013-11-26clk: tegra: move some PLLC and PLLXC init to clk-pll.cPeter De Schrijver2-93/+111
2013-11-26clk: tegra: Add TEGRA_PERIPH_NO_DIV flagPeter De Schrijver2-3/+9
2013-11-26clk: tegra: common periph_clk_enb_refcnt and clksPeter De Schrijver6-108/+85
2013-11-26clk: tegra: simplify periph clock dataPeter De Schrijver7-584/+464
2013-11-26clk: tegra: Fix clock rate computationThierry Reding1-0/+2
2013-11-26clk: tegra114: Rename gr_2d/gr_3d to gr2d/gr3dThierry Reding1-4/+4
2013-11-26clk: tegra: PLLE spread spectrum controlPeter De Schrijver1-1/+29
2013-11-26clk: tegra: Set the clk parent of host1x to pll_pAndrew Chew1-0/+1
2013-11-26clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clksPeter De Schrijver2-33/+39
2013-11-25clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2Mark Zhang1-0/+3