index
:
kernel/linux.git
linux-2.6.11.y
linux-2.6.12.y
linux-2.6.13.y
linux-2.6.14.y
linux-2.6.15.y
linux-2.6.16.y
linux-2.6.17.y
linux-2.6.18.y
linux-2.6.19.y
linux-2.6.20.y
linux-2.6.21.y
linux-2.6.22.y
linux-2.6.23.y
linux-2.6.24.y
linux-2.6.25.y
linux-2.6.26.y
linux-2.6.27.y
linux-2.6.28.y
linux-2.6.29.y
linux-2.6.30.y
linux-2.6.31.y
linux-2.6.32.y
linux-2.6.33.y
linux-2.6.34.y
linux-2.6.35.y
linux-2.6.36.y
linux-2.6.37.y
linux-2.6.38.y
linux-2.6.39.y
linux-3.0.y
linux-3.1.y
linux-3.10.y
linux-3.11.y
linux-3.12.y
linux-3.13.y
linux-3.14.y
linux-3.15.y
linux-3.16.y
linux-3.17.y
linux-3.18.y
linux-3.19.y
linux-3.2.y
linux-3.3.y
linux-3.4.y
linux-3.5.y
linux-3.6.y
linux-3.7.y
linux-3.8.y
linux-3.9.y
linux-4.0.y
linux-4.1.y
linux-4.10.y
linux-4.11.y
linux-4.12.y
linux-4.13.y
linux-4.14.y
linux-4.15.y
linux-4.16.y
linux-4.17.y
linux-4.18.y
linux-4.19.y
linux-4.2.y
linux-4.20.y
linux-4.3.y
linux-4.4.y
linux-4.5.y
linux-4.6.y
linux-4.7.y
linux-4.8.y
linux-4.9.y
linux-5.0.y
linux-5.1.y
linux-5.10.y
linux-5.11.y
linux-5.12.y
linux-5.13.y
linux-5.14.y
linux-5.15.y
linux-5.16.y
linux-5.17.y
linux-5.18.y
linux-5.19.y
linux-5.2.y
linux-5.3.y
linux-5.4.y
linux-5.5.y
linux-5.6.y
linux-5.7.y
linux-5.8.y
linux-5.9.y
linux-6.0.y
linux-6.1.y
linux-6.10.y
linux-6.2.y
linux-6.3.y
linux-6.4.y
linux-6.5.y
linux-6.6.y
linux-6.7.y
linux-6.8.y
linux-6.9.y
linux-rockchip-6.1.y
linux-rockchip-6.5.y
linux-rolling-lts
linux-rolling-stable
master
Linux kernel stable tree (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
drivers
/
cxl
/
core
Age
Commit message (
Expand
)
Author
Files
Lines
2023-10-28
cxl/pci: Add RCH downstream port error logging
Terry Bowman
1
-0
/
+96
2023-10-28
cxl/pci: Map RCH downstream AER registers for logging protocol errors
Terry Bowman
1
-0
/
+36
2023-10-28
cxl/pci: Update CXL error logging to use RAS register address
Terry Bowman
1
-13
/
+31
2023-10-28
PCI/AER: Refactor cper_print_aer() for use by CXL driver module
Terry Bowman
1
-0
/
+1
2023-10-28
cxl/pci: Add RCH downstream port AER register discovery
Robert Richter
3
-0
/
+52
2023-10-28
cxl/port: Remove Component Register base address from struct cxl_port
Robert Richter
1
-3
/
+1
2023-10-28
cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
Robert Richter
2
-36
/
+41
2023-10-28
cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_s...
Robert Richter
1
-0
/
+2
2023-10-28
cxl/port: Pre-initialize component register mappings
Robert Richter
1
-5
/
+7
2023-10-28
cxl/port: Rename @comp_map to @reg_map in struct cxl_register_map
Robert Richter
1
-3
/
+3
2023-10-28
cxl/port: Fix @host confusion in cxl_dport_setup_regs()
Dan Williams
1
-12
/
+31
2023-10-28
cxl/core/regs: Rename @dev to @host in struct cxl_register_map
Robert Richter
3
-17
/
+17
2023-10-28
cxl/port: Fix delete_endpoint() vs parent unregistration race
Dan Williams
1
-15
/
+19
2023-09-23
cxl/port: Fix cxl_test register enumeration regression
Dan Williams
1
-4
/
+9
2023-09-15
cxl/region: Refactor granularity select in cxl_port_setup_targets()
Alison Schofield
1
-9
/
+8
2023-09-15
cxl/region: Match auto-discovered region decoders by HPA range
Alison Schofield
1
-1
/
+23
2023-09-14
cxl/mbox: Fix CEL logic for poison and security commands
Ira Weiny
1
-11
/
+12
2023-07-28
cxl/memdev: Only show sanitize sysfs files when supported
Davidlohr Bueso
2
-1
/
+63
2023-06-30
cxl: Fix one kernel-doc comment
Yang Li
1
-1
/
+1
2023-06-26
Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl
Dan Williams
6
-84
/
+239
2023-06-26
Merge branch 'for-6.5/cxl-perf' into for-6.5/cxl
Dan Williams
5
-6
/
+141
2023-06-26
Merge branch 'for-6.5/cxl-region-fixes' into for-6.5/cxl
Dan Williams
1
-39
/
+63
2023-06-26
Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxl
Dan Williams
8
-262
/
+302
2023-06-26
Merge branch 'for-6.5/cxl-fwupd' into for-6.5/cxl
Dan Williams
1
-0
/
+308
2023-06-26
Merge branch 'for-6.5/cxl-background' into for-6.5/cxl
Dan Williams
2
-1
/
+199
2023-06-26
cxl: add a firmware update mechanism using the sysfs firmware loader
Vishal Verma
1
-0
/
+308
2023-06-26
cxl/mem: Support Secure Erase
Davidlohr Bueso
2
-1
/
+33
2023-06-26
cxl/mem: Wire up Sanitization support
Davidlohr Bueso
2
-0
/
+122
2023-06-26
cxl/mbox: Add sanitization handling machinery
Davidlohr Bueso
1
-0
/
+10
2023-06-26
cxl/mem: Introduce security state sysfs file
Davidlohr Bueso
1
-0
/
+33
2023-06-26
Revert "cxl/port: Enable the HDM decoder capability for switch ports"
Dan Williams
1
-23
/
+4
2023-06-26
cxl/memdev: Formalize endpoint port linkage
Dan Williams
3
-5
/
+6
2023-06-26
cxl/region: Manage decoder target_type at decoder-attach time
Dan Williams
1
-0
/
+12
2023-06-26
cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEM
Dan Williams
1
-9
/
+26
2023-06-26
cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}
Dan Williams
3
-9
/
+10
2023-06-26
cxl/memdev: Make mailbox functionality optional
Dan Williams
2
-1
/
+10
2023-06-26
cxl/mbox: Move mailbox related driver state to its own data structure
Dan Williams
2
-150
/
+163
2023-06-26
cxl/regs: Clarify when a 'struct cxl_register_map' is input vs output
Dan Williams
1
-4
/
+4
2023-06-25
cxl/region: Fix state transitions after reset failure
Dan Williams
1
-11
/
+15
2023-06-25
cxl/region: Flag partially torn down regions as unusable
Dan Williams
1
-0
/
+12
2023-06-25
cxl/region: Move cache invalidation before region teardown, and before setup
Dan Williams
1
-29
/
+37
2023-06-25
cxl/port: Store the downstream port's Component Register mappings in struct c...
Robert Richter
1
-0
/
+11
2023-06-25
cxl/port: Store the port's Component Register mappings in struct cxl_port
Robert Richter
1
-0
/
+27
2023-06-25
cxl/pci: Early setup RCH dport component registers from RCRB
Robert Richter
1
-0
/
+7
2023-06-25
cxl/regs: Remove early capability checks in Component Register setup
Robert Richter
1
-8
/
+0
2023-06-25
cxl/port: Remove Component Register base address from struct cxl_dport
Robert Richter
1
-1
/
+0
2023-06-25
cxl/pci: Refactor component register discovery for reuse
Terry Bowman
1
-0
/
+77
2023-06-25
cxl/core/regs: Add @dev to cxl_register_map
Robert Richter
2
-8
/
+14
2023-06-25
cxl: Rename 'uport' to 'uport_dev'
Dan Williams
3
-53
/
+60
2023-06-25
cxl: Rename member @dport of struct cxl_dport to @dport_dev
Robert Richter
2
-12
/
+12
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