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2023-09-03Merge tag 'dmaengine-6.6-rc1' of ↵Linus Torvalds64-2771/+765
git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine Pull dmaengine updates from Vinod Koul: "New controller support and updates to drivers. New support: - Qualcomm SM6115 and QCM2290 dmaengine support - at_xdma support for microchip,sam9x7 controller Updates: - idxd updates for wq simplification and ats knob updates - fsl edma updates for v3 support - Xilinx AXI4-Stream control support - Yaml conversion for bcm dma binding" * tag 'dmaengine-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (53 commits) dmaengine: fsl-edma: integrate v3 support dt-bindings: fsl-dma: fsl-edma: add edma3 compatible string dmaengine: fsl-edma: move tcd into struct fsl_dma_chan dmaengine: fsl-edma: refactor chan_name setup and safety dmaengine: fsl-edma: move clearing of register interrupt into setup_irq function dmaengine: fsl-edma: refactor using devm_clk_get_enabled dmaengine: fsl-edma: simply ATTR_DSIZE and ATTR_SSIZE by using ffs() dmaengine: fsl-edma: move common IRQ handler to common.c dmaengine: fsl-edma: Remove enum edma_version dmaengine: fsl-edma: transition from bool fields to bitmask flags in drvdata dmaengine: fsl-edma: clean up EXPORT_SYMBOL_GPL in fsl-edma-common.c dmaengine: fsl-edma: fix build error when arch is s390 dmaengine: idxd: Fix issues with PRS disable sysfs knob dmaengine: idxd: Allow ATS disable update only for configurable devices dmaengine: xilinx_dma: Program interrupt delay timeout dmaengine: xilinx_dma: Use tasklet_hi_schedule for timing critical usecase dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit dmaengine: xilinx_dma: Increase AXI DMA transaction segment count dmaengine: xilinx_dma: Pass AXI4-Stream control words to dma client dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property ...
2023-08-22dmaengine: fsl-edma: integrate v3 supportFrank Li3-23/+453
Significant alterations have been made to the EDMA v3's register layout. Now, each channel possesses a separate address space, encapsulating all channel-related controls and statuses, including IRQs. There are changes in bit position definitions as well. However, the fundamental control flow remains analogous to the previous versions. EDMA v3 was utilized in imx8qm, imx93, and will be in forthcoming chips. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230821161617.2142561-13-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22dmaengine: fsl-edma: move tcd into struct fsl_dma_chanFrank Li4-28/+42
Relocates the tcd into the fsl_dma_chan structure. This adjustment reduces the need to reference back to fsl_edma_engine, paving the way for EDMA V3 support. Unified the edma_writel and edma_writew functions for accessing TCD (Transfer Control Descriptor) registers. A new macro is added that can automatically detect whether a 32-bit or 16-bit access should be used based on the structure field definition. This provide better support 64-bit TCD with future v5 version. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202305271951.gmRobs3a-lkp@intel.com/ Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230821161617.2142561-11-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22dmaengine: fsl-edma: refactor chan_name setup and safetyFrank Li2-3/+4
Relocated the setup of chan_name from setup_irq() to fsl_chan init. This change anticipates its future use in various locations. For increased safety, sprintf has been replaced with snprintf. In addition, The size of the fsl_chan->name[] array was expanded from 16 to 32. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230821161617.2142561-10-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22dmaengine: fsl-edma: move clearing of register interrupt into setup_irq functionFrank Li1-1/+4
This accommodates differences in the register layout of EDMA v3 by moving the clearing of register interrupts into the platform-specific set_irq function. This should ensure better compatibility with EDMA v3. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230821161617.2142561-9-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22dmaengine: fsl-edma: refactor using devm_clk_get_enabledFrank Li1-17/+2
Use devm_clk_get_enabled in probe code to reduce error checks, thereby enhancing readability Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230821161617.2142561-8-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22dmaengine: fsl-edma: simply ATTR_DSIZE and ATTR_SSIZE by using ffs()Frank Li2-23/+8
Removes all ATTR_DSIZE_*BIT(BYTE) and ATTR_SSIZE_*BIT(BYTE) definitions in edma. Uses ffs() instead, as it gives identical results. This simplifies the code and avoids adding more similar definitions in future V3 version. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230821161617.2142561-7-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22dmaengine: fsl-edma: move common IRQ handler to common.cFrank Li4-56/+37
Move the common part of IRQ handler from fsl-edma-main.c and mcf-edma-main.c to fsl-edma-common.c. This eliminates redundant code, as the both files contains mostly identical code. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230821161617.2142561-6-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22dmaengine: fsl-edma: Remove enum edma_versionFrank Li4-41/+26
The enum edma_version, which defines v1, v2, and v3, is a software concept used to distinguish IP differences. However, it is not aligned with the chip reference manual. According to the 7ulp reference manual, it should be edma2. In the future, there will be edma3, edma4, and edma5, which could cause confusion. To avoid this confusion, remove the edma_version and instead use drvdata->flags to distinguish the IP difference. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230821161617.2142561-5-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22dmaengine: fsl-edma: transition from bool fields to bitmask flags in drvdataFrank Li3-6/+7
Replace individual bool fields with bitmask flags within drvdata. This will facilitate future extensions, making it easier to add more flags to accommodate new versions of the edma IP. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20230821161617.2142561-4-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22dmaengine: fsl-edma: clean up EXPORT_SYMBOL_GPL in fsl-edma-common.cFrank Li4-19/+4
Exported functions in fsl-edma-common.c are only used within fsl-edma.c and mcf-edma.c. Global export is unnecessary. This commit removes all EXPORT_SYMBOL_GPL in fsl-edma-common.c, and renames fsl-edma.c and mcf-edma.c to maintain the same final module names as before, thereby simplifying the codebase. Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20230821161617.2142561-3-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22dmaengine: fsl-edma: fix build error when arch is s390Frank Li1-0/+1
fixed build error reported by kernel test robot. >> s390-linux-ld: fsl-edma-main.c:(.text+0xf4c): undefined reference to `devm_platform_ioremap_resource' s390-linux-ld: drivers/dma/idma64.o: in function `idma64_platform_probe': Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202306210131.zaHVasxz-lkp@intel.com/ Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230821161617.2142561-2-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: idxd: Fix issues with PRS disable sysfs knobFenghua Yu1-2/+2
There are two issues in the current PRS disable sysfs store function wq_prs_disable_store(): 1. Since PRS disable knob is invisible if PRS disable is not supported in WQ, it's redundant to check PRS support again in the store function again. Remove the redundant PRS support check. 2. Since PRS disable is read-only when the device is not configurable, PRS disable cannot be changed on the device. Add device configurable check in the store function. Fixes: f2dc327131b5 ("dmaengine: idxd: add per wq PRS disable") Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20230811012635.535413-2-fenghua.yu@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: idxd: Allow ATS disable update only for configurable devicesFenghua Yu1-0/+4
ATS disable status in a WQ is read-only if the device is not configurable. This change ensures that the ATS disable attribute can be modified via sysfs only on configurable devices. Fixes: 92de5fa2dc39 ("dmaengine: idxd: add ATS disable knob for work queues") Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20230811012635.535413-1-fenghua.yu@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: xilinx_dma: Program interrupt delay timeoutRadhey Shyam Pandey1-9/+11
Program IRQDelay for AXI DMA. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. It enables dmaengine to respond in real-time even though interrupt coalescing is configured. It also remove the placeholder for delay interrupt and merge it with frame completion interrupt. Since by default interrupt delay timeout is disabled this feature addition has no functional impact on VDMA, MCDMA and CDMA IP's. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://lore.kernel.org/r/1691387509-2113129-8-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: xilinx_dma: Use tasklet_hi_schedule for timing critical usecaseRadhey Shyam Pandey1-1/+1
Schedule tasklet with high priority to ensure that callback processing is prioritized. It improves throughput for netdev dma clients. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://lore.kernel.org/r/1691387509-2113129-7-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: xilinx_dma: Freeup active list based on descriptor completion bitRadhey Shyam Pandey1-0/+9
AXIDMA IP in SG mode sets completion bit to 1 when the transfer is completed. Read this bit to move descriptor from active list to the done list. This feature is needed when interrupt delay timeout and IRQThreshold is enabled i.e Dly_IrqEn is triggered w/o completing interrupt threshold. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://lore.kernel.org/r/1691387509-2113129-6-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: xilinx_dma: Increase AXI DMA transaction segment countRadhey Shyam Pandey1-1/+1
Increase AXI DMA transaction segments count to ensure that even in high load we always get a free segment in prepare descriptor for a DMA_SLAVE transaction. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://lore.kernel.org/r/1691387509-2113129-5-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: xilinx_dma: Pass AXI4-Stream control words to dma clientRadhey Shyam Pandey1-0/+37
Read DT property to check if AXI DMA is connected to streaming IP i.e axiethernet. If connected i.e xlnx,axistream-connected property is present in the dma node then pass AXI4-Stream control words to dma client using metadata_ops dmaengine API. If not connected then driver won't support metadata_ops dmaengine API and continue to support all legacy usecases. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://lore.kernel.org/r/1691387509-2113129-4-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: ioatdma: use pci_dev_id() to simplify the codeJialin Zhang1-1/+1
PCI core API pci_dev_id() can be used to get the BDF number for a pci device. We don't need to compose it mannually. Use pci_dev_id() to simplify the code a little bit. Signed-off-by: Jialin Zhang <zhangjialin11@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20230815023821.3518007-1-zhangjialin11@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: ioat: fixing the wrong dma_dev->chancntYajun Deng2-9/+11
The chancnt would be updated in __dma_async_device_channel_register(), but it was assigned in ioat_enumerate_channels(). Therefore chancnt has the wrong value. Add chancnt member to the struct ioatdma_device, ioat_dma->chancnt is used in ioat, dma_dev->chancnt is used in dmaengine. Signed-off-by: Yajun Deng <yajun.deng@linux.dev> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20230815061151.2724474-1-yajun.deng@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: Simplify dma_async_device_register()Yajun Deng1-62/+20
There are a lot of duplicate codes for checking if the dma has some capability. Define a temporary macro that is used to check if the dma claims some capability and if the corresponding function is implemented. Signed-off-by: Yajun Deng <yajun.deng@linux.dev> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20230815072346.2798927-1-yajun.deng@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: fsl-edma: use struct_size() helperYu Liao1-4/+3
Make use of the struct_size() helper instead of an open-coded version, in order to avoid any potential type mistakes or integer overflows that, in the worst scenario, could lead to heap overflows. Signed-off-by: Yu Liao <liaoyu15@huawei.com> Link: https://lore.kernel.org/r/20230821073600.4078584-1-liaoyu15@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21Merge branches 'apple/dart', 'arm/mediatek', 'arm/renesas', 'arm/rockchip', ↵Joerg Roedel5-38/+76
'arm/smmu', 'unisoc', 'x86/vt-d', 'x86/amd' and 'core' into next
2023-08-21dmaengine: mcf-edma: Use struct_size()Christophe JAILLET1-4/+3
Use struct_size() instead of hand writing it. This is less verbose and more informative. 'mcf_chan' is now unused and can be removed. In fact, it is shadowed by another variable in the 'for' loop below. Keep this one. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/97c2bb1c9b69d0739da3762a7752ae6582c4ad02.1683390112.git.christophe.jaillet@wanadoo.fr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: lgm: Use builtin_platform_driver macro to simplify the codeLi Zetao1-6/+1
Use the builtin_platform_driver macro to simplify the code, which is the same as declaring with device_initcall(). Signed-off-by: Li Zetao <lizetao1@huawei.com> Acked-by: Peter Harliman Liem <pliem@maxlinear.com> Link: https://lore.kernel.org/r/20230815080250.1089589-1-lizetao1@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: ste_dma40: Add missing IRQ check in d40_proberuanjinjie1-0/+4
Check for the return value of platform_get_irq(): if no interrupt is specified, it wouldn't make sense to call request_irq(). Fixes: 8d318a50b3d7 ("DMAENGINE: Support for ST-Ericssons DMA40 block v3") Signed-off-by: Ruan Jinjie <ruanjinjie@huawei.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230724144108.2582917-1-ruanjinjie@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: owl-dma: fix clang -Wvoid-pointer-to-enum-cast warningJustin Stitt1-1/+1
When building with clang 18 I see the following warning: | drivers/dma/owl-dma.c:1119:14: warning: cast to smaller integer type | 'enum owl_dma_id' from 'const void *' [-Wvoid-pointer-to-enum-cast] | 1119 | od->devid = (enum owl_dma_id)of_device_get_match_data(&pdev->dev); This is due to the fact that `of_device_get_match_data()` returns a void* while `enum owl_dma_id` has the size of an int. Cast result of `of_device_get_match_data()` to a uintptr_t to silence the above warning for clang builds using W=1 Link: https://github.com/ClangBuiltLinux/linux/issues/1910 Reported-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Justin Stitt <justinstitt@google.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/r/20230816-void-drivers-dma-owl-dma-v1-1-a0a5e085e937@google.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-21dmaengine: idxd: Remove unused declarationsYue Haibing1-5/+0
Commit c05257b5600b ("dmanegine: idxd: open code the dsa_drv registration") removed idxd_{un}register_driver() definitions but not the declarations. Commit 034b3290ba25 ("dmaengine: idxd: create idxd_device sub-driver") declared idxd_{un}register_idxd_drv() but never implemented it. Commit 8f47d1a5e545 ("dmaengine: idxd: connect idxd to dmaengine subsystem") declared idxd_parse_completion_status() but never implemented it. Signed-off-by: Yue Haibing <yuehaibing@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Fenghua Yu <fenghua.yu@intel.com> Link: https://lore.kernel.org/r/20230817114135.50264-1-yuehaibing@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-09dmaengine/idxd: Re-enable kernel workqueue under DMA APIJacob Pan5-38/+76
Kernel workqueues were disabled due to flawed use of kernel VA and SVA API. Now that we have the support for attaching PASID to the device's default domain and the ability to reserve global PASIDs from SVA APIs, we can re-enable the kernel work queues and use them under DMA API. We also use non-privileged access for in-kernel DMA to be consistent with the IOMMU settings. Consequently, interrupt for user privilege is enabled for work completion IRQs. Link: https://lore.kernel.org/linux-iommu/20210511194726.GP1002214@nvidia.com/ Tested-by: Tony Zhu <tony.zhu@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Fenghua Yu <fenghua.yu@intel.com> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Link: https://lore.kernel.org/r/20230802212427.1497170-9-jacob.jun.pan@linux.intel.com Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2023-08-06dmaengine: xilinx: xdma: Fix typoMiquel Raynal1-1/+1
Probably a copy/paste error with the previous block, here we are actually managing C2H IRQs. Fixes: 17ce252266c7 ("dmaengine: xilinx: xdma: Add xilinx xdma driver") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20230731101442.792514-3-miquel.raynal@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-06dmaengine: xilinx: xdma: Fix interrupt vector settingMiquel Raynal1-0/+2
A couple of hardware registers need to be set to reflect which interrupts have been allocated to the device. Each register is 32-bit wide and can receive four 8-bit values. If we provide any other interrupt number than four, the irq_num variable will never be 0 within the while check and the while block will loop forever. There is an easy way to prevent this: just break the for loop when we reach "irq_num == 0", which anyway means all interrupts have been processed. Cc: stable@vger.kernel.org Fixes: 17ce252266c7 ("dmaengine: xilinx: xdma: Add xilinx xdma driver") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Lizhi Hou <lizhi.hou@amd.com> Link: https://lore.kernel.org/r/20230731101442.792514-2-miquel.raynal@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-06dmaengine: owl-dma: Modify mismatched function nameZhang Jianhua1-1/+1
No functional modification involved. drivers/dma/owl-dma.c:208: warning: expecting prototype for struct owl_dma_pchan. Prototype was for struct owl_dma_vchan instead HDRTEST usr/include/sound/asequencer.h Fixes: 47e20577c24d ("dmaengine: Add Actions Semi Owl family S900 DMA driver") Signed-off-by: Zhang Jianhua <chris.zjh@huawei.com> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Link: https://lore.kernel.org/r/20230722153244.2086949-1-chris.zjh@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-06dmaengine: idxd: Clear PRS disable flag when disabling IDXD deviceFenghua Yu1-3/+1
Disabling IDXD device doesn't reset Page Request Service (PRS) disable flag to its initial value 0. This may cause user confusion because once PRS is disabled user will see PRS still remains the previous setting (i.e. disabled) via sysfs interface even after the device is disabled. To eliminate user confusion, reset PRS disable flag to ensure that the PRS flag bit reflects correct state after the device is disabled. Additionally, simplify the code by setting wq->flags to 0, which clears all flag bits, including any future additions. Fixes: f2dc327131b5 ("dmaengine: idxd: add per wq PRS disable") Tested-by: Tony Zhu <tony.zhu@intel.com> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20230712193505.3440752-1-fenghua.yu@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-06dmaengine: pl330: Return DMA_PAUSED when transaction is pausedIlpo Järvinen1-2/+16
pl330_pause() does not set anything to indicate paused condition which causes pl330_tx_status() to return DMA_IN_PROGRESS. This breaks 8250 DMA flush after the fix in commit 57e9af7831dc ("serial: 8250_dma: Fix DMA Rx rearm race"). The function comment for pl330_pause() claims pause is supported but resume is not which is enough for 8250 DMA flush to work as long as DMA status reports DMA_PAUSED when appropriate. Add PAUSED state for descriptor and mark BUSY descriptors with PAUSED in pl330_pause(). Return DMA_PAUSED from pl330_tx_status() when the descriptor is PAUSED. Reported-by: Richard Tresidder <rtresidd@electromag.com.au> Tested-by: Richard Tresidder <rtresidd@electromag.com.au> Fixes: 88987d2c7534 ("dmaengine: pl330: add DMA_PAUSE feature") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/linux-serial/f8a86ecd-64b1-573f-c2fa-59f541083f1a@electromag.com.au/ Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Link: https://lore.kernel.org/r/20230526105434.14959-1-ilpo.jarvinen@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-06dmaengine: mcf-edma: Fix a potential un-allocated memory accessChristophe JAILLET1-6/+7
When 'mcf_edma' is allocated, some space is allocated for a flexible array at the end of the struct. 'chans' item are allocated, that is to say 'pdata->dma_channels'. Then, this number of item is stored in 'mcf_edma->n_chans'. A few lines later, if 'mcf_edma->n_chans' is 0, then a default value of 64 is set. This ends to no space allocated by devm_kzalloc() because chans was 0, but 64 items are read and/or written in some not allocated memory. Change the logic to define a default value before allocating the memory. Fixes: e7a3ff92eaf1 ("dmaengine: fsl-edma: add ColdFire mcf5441x edma support") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/f55d914407c900828f6fad3ea5fa791a5f17b9a4.1685172449.git.christophe.jaillet@wanadoo.fr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-01dmaengine: ep93xx: Use struct_size()Christophe JAILLET1-3/+1
Use struct_size() instead of hand-writing it, when allocating a structure with a flex array. This is less verbose, more robust and more informative. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/36fa11d95b448b5f3f1677da41fe35b9e2751427.1690041500.git.christophe.jaillet@wanadoo.fr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-01dmaengine: Explicitly include correct DT includesRob Herring39-43/+46
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230718143138.1066177-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-01dmaengine: idxd: Expose ATS disable knob only when WQ ATS is supportedFenghua Yu1-4/+3
WQ Advanced Translation Service (ATS) can be controlled only when WQ ATS is supported. The sysfs ATS disable knob should be visible only when the features is supported. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20230712174436.3435088-2-fenghua.yu@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-01dmaengine: idxd: Simplify WQ attribute visibility checksFenghua Yu1-15/+5
The functions that check if WQ attributes are invisible are almost duplicate. Define a helper to simplify these functions and future WQ attribute visibility checks as well. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20230712174436.3435088-1-fenghua.yu@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-01dmaengine:idxd: Use local64_try_cmpxchg in perfmon_pmu_event_updateUros Bizjak1-4/+3
Use local64_try_cmpxchg instead of local64_cmpxchg (*ptr, old, new) == old in perfmon_pmu_event_update. x86 CMPXCHG instruction returns success in ZF flag, so this change saves a compare after cmpxchg (and related move instruction in front of cmpxchg). Also, try_cmpxchg implicitly assigns old *ptr value to "old" when cmpxchg fails. There is no need to re-read the value in the loop. No functional change intended. Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: Dave Jiang <dave.jiang@intel.com> Cc: Vinod Koul <vkoul@kernel.org> Signed-off-by: Uros Bizjak <ubizjak@gmail.com> Reviewed-by: Tom Zanussi <tom.zanussi@linux.intel.com> Link: https://lore.kernel.org/r/20230703145346.5206-1-ubizjak@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-01dmaengine: ipu: Remove the driverFabio Estevam6-2363/+0
The i.MX3 IPU driver does not support devicetree and i.MX has been converted to a DT-only platform since kernel 5.10. As there is no user for this driver anymore, just remove it. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20230729192945.1217206-1-festevam@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12dmaengine: xilinx: dma: remove arch dependencyZong Li1-1/+1
As following patches, xilinx dma is also now architecture agnostic, and it can be compiled for several architectures. We have verified the CDMA on RISC-V platform, let's remove the ARCH dependency list instead of adding new ARCH. To avoid breaking the s390 build, add a dependency on HAS_IOMEM. 'e8b6c54f6d57 ("net: xilinx: temac: Relax Kconfig dependencies")' 'd7eaf962a90b ("net: axienet: In kconfig remove arch dependency for axi_emac")' Signed-off-by: Zong Li <zong.li@sifive.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Suggested-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/20230531090141.23546-1-zong.li@sifive.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12dmaengine: idxd: No need to clear memory after a dma_alloc_coherent() callChristophe JAILLET1-2/+0
dma_alloc_coherent() already clear the allocated memory, there is no need to explicitly call memset(). Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by: Fenghua Yu <fenghua.yu@intel.com> Acked-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/f44be04317387f8936d31d5470963541615f30ef.1685283065.git.christophe.jaillet@wanadoo.fr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12dmaengine: idxd: Modify the dependence of attribute pasid_enabledRex Zhang1-1/+1
Kernel PASID and user PASID are separately enabled. User needs to know the user PASID enabling status to decide how to use IDXD device in user space. This is done via the attribute /sys/bus/dsa/devices/dsa0/pasid_enabled. It's unnecessary for user to know the kernel PASID enabling status because user won't use the kernel PASID. But instead of showing the user PASID enabling status, the attribute shows the kernel PASID enabling status. Fix the issue by showing the user PASID enabling status in the attribute. Fixes: 42a1b73852c4 ("dmaengine: idxd: Separate user and kernel pasid enabling") Signed-off-by: Rex Zhang <rex.zhang@intel.com> Acked-by: Fenghua Yu <fenghua.yu@intel.com> Acked-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/20230614062706.1743078-1-rex.zhang@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12dmaengine: mediatek: drop bogus pm_runtime_set_active()Johan Hovold1-1/+0
The runtime PM state must be updated while runtime PM is disabled for the change to take effect. Drop the bogus pm_runtime_set_active() which left the PM state set to suspended (as it should be or the clock would not be enabled when the device is resumed). Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230622075150.885-1-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12dmaengine: stm32-dma: Use devm_platform_get_and_ioremap_resource()Yangtao Li1-2/+1
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li <frank.li@vivo.com> Reviewed-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Tested-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20230705081856.13734-5-frank.li@vivo.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12dmaengine: shdmac: Convert to devm_platform_ioremap_resource()Yangtao Li1-4/+3
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230705081856.13734-4-frank.li@vivo.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12dmaengine: qcom: hidma_mgmt: Use devm_platform_get_and_ioremap_resource()Yangtao Li1-3/+2
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230705081856.13734-3-frank.li@vivo.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12dmaengine: qcom_hidma: Use devm_platform_get_and_ioremap_resource()Yangtao Li1-7/+5
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li <frank.li@vivo.com> Link: https://lore.kernel.org/r/20230705081856.13734-2-frank.li@vivo.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-31 21:38:43 +0300