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path: root/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
AgeCommit message (Expand)AuthorFilesLines
2024-07-01drm/amd/display: Move dio files into dio folderBhuvanachandra Pinninti1-749/+0
2024-04-27drm/amd/display: Add misc DC changes for DCN401Aurabindo Pillai1-2/+2
2024-04-27drm/amd/display: Add some DCN401 reg name to macro definitionsAurabindo Pillai1-0/+7
2024-04-17drm/amd/display: Rework dcn10_stream_encoder headerRodrigo Siqueira1-7/+3
2023-09-12drm/amd/display: fix some non-initialized register mask and settingCharlene Liu1-1/+4
2023-08-30drm/amd/display: Update DCN10 for DCN35 supportQingqing Zhuo1-2/+17
2022-07-05drm/amd/display: Program ACP related registerAlan Liu1-14/+2
2022-07-05drm/amd/display: Add function to set pixels per cycleEric Bernstein1-0/+1
2022-06-03drm/amd/display: add new pixel rate programmingJun Lei1-0/+1
2022-06-03drm/amd/display: Fix USBC link creationDillon Varone1-0/+3
2022-06-03drm/amd/display: Add dependant changes for DCN32/321Aurabindo Pillai1-0/+25
2022-04-26drm/amd/display: Add Audio readback registersIlya Bakoulin1-0/+8
2022-02-03drm/amd/display: revert "Reset fifo after enable otg"Zhan Liu1-3/+0
2021-11-22drm/amd/display: Reset fifo after enable otgXu, Jinze1-0/+3
2021-09-14drm/amd/display: Add DPCD writes at key pointsLeo (Hanghong) Ma1-0/+2
2021-06-16drm/amd/display: Add interface to get Calibrated Avg Level from FIFOWesley Chalmers1-0/+24
2020-12-15drm/amd/display: Add missing DP_SEC register definitions and masksMax Tseng1-0/+6
2020-11-05drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)Alex Deucher1-8/+0
2020-09-16drm/amd/display: Rename set_mst_bandwidth to align with DP specGeorge Shen1-1/+1
2020-08-11drm/amd/display: Switch to immediate mode for updating infopacketsAnthony Koo1-0/+14
2020-07-01drm/amd/display: Add DCN3 DIOBhawanpreet Lakha1-0/+42
2019-11-13drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTEDBhawanpreet Lakha1-8/+0
2019-11-13drm/amd/display: set MSA MISC1 bit 6 while sending colorimetry in VSC SDPAnthony Koo1-0/+1
2019-10-11drm/amd/display: add more checks to validate seamless boot timingMartin Leung1-0/+5
2019-08-15drm/amd/display: enabling seamless boot sequence for dcn2Martin Leung1-0/+3
2019-08-15drm/amd/display: reset hdmi tmds rate and data scramble on pipe resetWenjing Liu1-0/+3
2019-07-18drm/amd/display: Add DIG_CLOCK_PATTERN registerNevenko Stupar1-3/+7
2019-07-18drm/amd/display: Do not fill Null packet in the blank periodCharlene Liu1-0/+2
2019-07-18drm/amd/display:Use Pixel clock in 100Hz units for HDMI Audio wall clock DTONevenko Stupar1-2/+2
2019-06-22drm/amd/display: Add DCN2 DIOHarry Wentland1-0/+40
2019-05-31drm/amd/display: Refactor DIO stream encoderEric Bernstein1-0/+17
2019-05-24drm/amd/display: Expose send immediate sdp message interfaceLeo (Hanghong) Ma1-0/+22
2019-03-28drm/amd/display: Pass SDP spliting in parametersNikola Cornij1-1/+2
2019-01-26drm/amd/display: Connect dig_fe to otg directly instead of calling bioshersen wu1-2/+8
2018-08-27drm/amd/display: Define registers for dcn10Nikola Cornij1-0/+2
2018-04-11drm/amd/display: Make DCN stream encoder shareableEric Bernstein1-353/+293
2018-04-11drm/amd/display: Refactor stream encoder for HW reviewEric Bernstein1-0/+584
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-23 19:42:03 +0300