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path: root/drivers/gpu/drm/amd/display/dc/dcn303
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2022-03-15drm/amd/display: move FPU associated DCN303 code to DML folderJasdeep Dhillon3-343/+13
[Why & How] As part of the FPU isolation work documented in https://patchwork.freedesktop.org/series/93042/, isolate code that uses FPU in DCN303 to DML, where all FPU code should locate. Co-authored-by: Jasdeep Dhillon <jasdeep.dhillon@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Jasdeep Dhillon <jasdeep.dhillon@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-08drm/amdgpu: move dpcs_3_0_3 headers from dcn to dpcsAlex Deucher1-2/+2
To align with other headers. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-30drm/amd/display: Add reg defs for DCN303Wesley Chalmers1-2/+18
[WHY] These registers are currently missing from the DCN303 header files Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-30drm/amd/display: Changed pipe split policy to allow for multi-display pipe splitAngus Wang1-1/+1
[WHY] Current implementation of pipe split policy prevents pipe split with multiple displays connected, which caused the MCLK speed to be stuck at max [HOW] Changed the pipe split policies so that pipe split is allowed for multi-display configurations Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1522 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1709 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1655 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403 Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Angus Wang <angus.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-14drm/amd: append missing includesIsabella Basso1-0/+2
This fixes warnings caused by global functions lacking prototypes:, such as: warning: no previous prototype for 'dcn303_hw_sequencer_construct' [-Wmissing-prototypes] 12 | void dcn303_hw_sequencer_construct(struct dc *dc) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ... warning: no previous prototype for ‘amdgpu_has_atpx’ [-Wmissing-prototypes] 76 | bool amdgpu_has_atpx(void) { | ^~~~~~~~~~~~~~~ Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Isabella Basso <isabbasso@riseup.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-12-02drm/amd/display: Enable P010 for DCN3x ASICsStylon Wang1-1/+1
[Why + How] Enable P010 for SDR video applications. Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-22drm/amd/display: Fix LTTPR not EnabledAngus Wang1-0/+17
[WHY] Previous LTTPR change has caused a regression that led to an issue where LTTPR is disabled [HOW] Extended changes from previous fix to DCN30X Reviewed-by: Wesley Chalmers <wesley.chalmers@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Angus Wang <angus.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-22drm/amd/display: Revert changes for MPO underflowAngus Wang1-1/+1
[WHY] The previous changes for fixing MPO underflow with multiple display connected caused a regression where the machine runs into a hang when doing multiple driver pnp with multiple displays connected [HOW] Reverted offending change Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Angus Wang <angus.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-18drm/amd/display: Fix RGB MPO underflow with multiple displaysAngus Wang1-1/+1
[WHY] With RGB MPO enabled, playing a video with multiple displays connected results in underflow when closing the video window [HOW] Reverted the old change to fix this problem, which prevented pipe splits for multiple display configurations and caused high MCLK speeds during idle. Added a two step call to dc_update_planes_and_stream, first time with pipe split disabled and the second time with pipe split enabled, which fixed the underflow issue Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Angus Wang <angus.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-10-28drm/amd/display: Manually adjust strobe for DCN303Martin Leung1-0/+14
why: DCN303's 4 channel SOC BB causes problems at strobe how: workaround to manually adjust strobe calculation using FCLK restrict. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Agustin Gutierrez <agustin.gutierrez@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Martin Leung <Martin.Leung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-01drm/amd/display: add missing ABM register offsetsJosip Pavic1-1/+1
[Why] Some ABM registers don't exist on DCN 3.01, so are missing from its register offset list. However, this list was copied to later versions of DCN that do have these registers. As a result, they're inaccessible from the driver on those DCN versions even though they exist. [How] Add the missing ABM register offsets to DCN 3.02+ Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Josip Pavic <Josip.Pavic@amd.com> Tested-by: Daniel Wheeler <Daniel.Wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-31drm/amd/display: Fix memory leak reported by coverityAnson Jacob1-1/+5
Free memory allocated if any of the previous allocations failed. >>> CID 1487129: Resource leaks (RESOURCE_LEAK) >>> Variable "vpg" going out of scope leaks the storage it points to. Addresses-Coverity-ID: 1487129: ("Resource leaks") Reviewed-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Anson Jacob <Anson.Jacob@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-08-06drm/amd/display: Increase stutter watermark for dcn303Bing Guo1-2/+2
[Why&How] Hardware team suggested to use SRExitTime= 35.5us as w/a to prevent underflow in certain modes. Reviewed-by: Martin Leung <martin.leung@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Bing Guo <bing.guo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-21drm/amd/display: Populate dtbclk entries for dcn3.02/3.03Bindu Ramamurthy1-1/+5
[Why] Populate dtbclk values from bwparams for dcn302, dcn303. [How] dtbclk values are fetched from bandwidthparams for all DPM levels and for DPM levels where smu returns 0, previous level values are reported. Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-21drm/amd/display: Populate socclk entries for dcn3.02/3.03Bindu Ramamurthy1-2/+5
[Why] Initialize socclk entries in bandwidth params for dcn302, dcn303. [How] Fetch the sockclk values from smu for the DPM levels and for the DPM levels where smu returns 0, previous level values are reported. Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-22drm/amd/display: get socBB from VBIOS for dcn302 and dcn303Aurabindo Pillai1-0/+20
[why] Some SOC BB paramters may vary per SKU, and it does not make sense for driver to hardcode these values. This change was added for dcn30 and dcn301, but not for dcn302 and dcn303 [how] Parse the values from VBIOS if available, and use them if valid Fixes: 93669c8e480dca ("drm/amd/display: get socBB from VBIOS") Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-19drm/amd/display: Increase stutter watermark for dcn302 and dcn303Aurabindo Pillai1-2/+2
[Why] Current watermarks end up programming lowers watermarks which results in screen flickering and underflow for certain modes like 1440p. [How] Add 11us to stutter exit & stutter enter plus exit watermark. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-11drm/amd/display: add dummy PG callback for beige gobyAurabindo Pillai3-0/+7
[Why&How] PG registers are absent in beige goby, so programming these registers generate call trace. Fix this by adding a dummy function in dcn303 initialization function which prevents writing to non existant registers. Fixes: cd6d421e3d1ad5 ("drm/amd/display: Initial DC support for Beige Goby") Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-08drm/amd/display: Change default policy for MPO with multidisplayAric Cyr1-1/+1
[Why] Rearranging pipes with multiple displays and multiple planes cannot be done atomically and requires a much improved sequence to deal with it. [How] To workaround such issues, prefer avoid pipe-split policy for multidisplay scenarios. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amd/display: enable idle optimizations for beige gobyAurabindo Pillai1-0/+1
[Why&How] MALL requires idle optimizations to be enabled. This enables MALL feature on dcn303 Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amd/display: Update DCN303 SR Exit LatencyJoshua Aberback1-1/+1
[Why] This update was made for DCN30, but it is needed for DCN303 as well Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amd/display: Add callback for update_soc_for_wm_a for dcn303Aurabindo Pillai1-0/+1
[Why&How] Absense of this callback causes null pointer dereference. Add the corresponding callback in dcn303 resources. Fixes: 443dfba0248387 ("drm/amd/display: fix dcn3+ bw validation soc param update sequence") Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amd/display: Edit license info for beige goby DC filesAurabindo Pillai8-146/+16
[How] * Add MIT license to all new files as SPDX tag. * Fix copyright year Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amd/display: Initial DC support for Beige GobyAurabindo Pillai8-0/+1980
[Why&How] Add Beige Goby (DCN303) resource, irq service, & dmub loader. v2: fix nbio include (Alex) Signed-off-by: Chris Park <Chris.Park@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-10-19 04:06:06 +0300