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path: root/drivers/gpu/drm/amd/display/dc
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5 daysminmax: make generic MIN() and MAX() macros available everywhereLinus Torvalds1-0/+2
This just standardizes the use of MIN() and MAX() macros, with the very traditional semantics. The goal is to use these for C constant expressions and for top-level / static initializers, and so be able to simplify the min()/max() macros. These macro names were used by various kernel code - they are very traditional, after all - and all such users have been fixed up, with a few different approaches: - trivial duplicated macro definitions have been removed Note that 'trivial' here means that it's obviously kernel code that already included all the major kernel headers, and thus gets the new generic MIN/MAX macros automatically. - non-trivial duplicated macro definitions are guarded with #ifndef This is the "yes, they define their own versions, but no, the include situation is not entirely obvious, and maybe they don't get the generic version automatically" case. - strange use case #1 A couple of drivers decided that the way they want to describe their versioning is with #define MAJ 1 #define MIN 2 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) which adds zero value and I just did my Alexander the Great impersonation, and rewrote that pointless Gordian knot as #define DRV_VERSION "1.2" instead. - strange use case #2 A couple of drivers thought that it's a good idea to have a random 'MIN' or 'MAX' define for a value or index into a table, rather than the traditional macro that takes arguments. These values were re-written as C enum's instead. The new function-line macros only expand when followed by an open parenthesis, and thus don't clash with enum use. Happily, there weren't really all that many of these cases, and a lot of users already had the pattern of using '#ifndef' guarding (or in one case just using '#undef MIN') before defining their own private version that does the same thing. I left such cases alone. Cc: David Laight <David.Laight@aculab.com> Cc: Lorenzo Stoakes <lorenzo.stoakes@oracle.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
9 daysdrm/amd/display: Remove ASSERT if significance is zero in math_ceil2Rodrigo Siqueira1-2/+0
In the DML math_ceil2 function, there is one ASSERT if the significance is equal to zero. However, significance might be equal to zero sometimes, and this is not an issue for a ceil function, but the current ASSERT will trigger warnings in those cases. This commit removes the ASSERT if the significance is equal to zero to avoid unnecessary noise. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com> Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 332315885d3ccc6d8fe99700f3c2e4c24aa65ab7)
9 daysdrm/amd/display: Check for NULL pointerSung Joon Kim1-1/+2
[why & how] Need to make sure plane_state is initialized before accessing its members. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Xi (Alex) Liu <xi.liu@amd.com> Signed-off-by: Sung Joon Kim <sungjoon.kim@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 295d91cbc700651782a60572f83c24861607b648)
2024-07-18drm/amd/display: fix corruption with high refresh rates on DCN 3.0Alex Deucher2-12/+13
This reverts commit bc87d666c05a13e6d4ae1ddce41fc43d2567b9a2 and the register changes from commit 6d4279cb99ac4f51d10409501d29969f687ac8dc. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3412 Cc: mikhail.v.gavrilov@gmail.com Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 6.10.x
2024-07-16drm/amd/display: Add simple struct doc to remove doc build warningRodrigo Siqueira2-5/+32
This commit is a part of a series that addresses the following build warning for opp: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.h:1: warning: no structured comments found ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h:1: warning: no structured comments found This commit fixes this issue by adding a simple kernel-doc to a struct in the opp.h and the dpp.h files. Cc: Alex Deucher <alexander.deucher@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-16drm/amd/display: Move DIO documentation to the right placeRodrigo Siqueira2-9/+29
When building the kernel-doc, it complains with the below warning: ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h:1: warning: no structured comments found ./drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h:1: warning: no structured comments found This warning was caused by the wrong use of the ':export:' and the lack of function documentation in the file pointed under the ':internal:'. This commit addresses those issues by relocating the overview documentation to the correct C file, removing the ':export:' options, and adding two simple kernel-doc to ensure that ':internal:' does not have any warning. Cc: Alex Deucher <alexander.deucher@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Link: https://lore.kernel.org/dri-devel/20240715085918.68f5ecc9@canb.auug.org.au/ Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-16drm/amd/display: Add doc entry for program_3dlut_sizeAlex Hung1-0/+14
Fixes the warning: Function parameter or struct member 'program_3dlut_size' not described in 'mpc_funcs' Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Closes: https://lore.kernel.org/dri-devel/20240715090445.7e9387ec@canb.auug.org.au/ Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-03drm/amd/display: Fix warning comparing pointer to 0Jiapeng Chong1-1/+1
Avoid pointer type value compared with 0 to make code clear. ./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c:14:12-13: WARNING comparing pointer to 0. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9458 Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-03drm/amd/display: Fix warning comparing pointer to 0Jiapeng Chong1-1/+1
Avoid pointer type value compared with 0 to make code clear. ./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c:24:12-13: WARNING comparing pointer to 0. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9458 Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-03drm/amd/display: Fix warning comparing pointer to 0Jiapeng Chong1-1/+1
Avoid pointer type value compared with 0 to make code clear. ./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c:19:12-13: WARNING comparing pointer to 0. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9458 Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-03drm/amd/display: Fix warning comparing pointer to 0Jiapeng Chong1-1/+1
Avoid pointer type value compared with 0 to make code clear. ./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c:31:12-13: WARNING comparing pointer to 0. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9458 Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-03drm/amd/display: Fix unsigned comparison with less than zeroJiapeng Chong1-9/+6
The return value from the call to dml21_find_dc_pipes_for_plane() is int. However, the return value is being assigned to an unsigned int variable 'num_pipes', the condition if(num_pipes <= 0) is not rigorous enough, so making 'num_pipes' an int. ./drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c:318:6-15: WARNING: Unsigned expression compared with zero: num_pipes <= 0. ./drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c:360:6-15: WARNING: Unsigned expression compared with zero: num_pipes <= 0. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9454 Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: 3.2.291Aric Cyr1-1/+1
* FW Release 0.0.224.0 * Fix bw issue for dcn351 * Fix FAMS2 logic issue for dcn401 * Fix Coverity issues * Fix cursor issues * Refactor dio sources Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Fix array-index-out-of-bounds in dml2/FCLKChangeSupportRoman Li1-1/+1
[Why] Potential out of bounds access in dml2_calculate_rq_and_dlg_params() because the value of out_lowest_state_idx used as an index for FCLKChangeSupport array can be greater than 1. [How] Currently dml2 core specifies identical values for all FCLKChangeSupport elements. Always use index 0 in the condition to avoid out of bounds access. Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Update efficiency bandwidth for dcn351Fangzhi Zuo1-0/+1
Fix 4k240 underflow on dcn351 Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: replace CRTC disable function callXi (Alex) Liu1-2/+2
[Why] In OTG disable workarund, CRTC is disabled immediately to improve performance, but this may cause timing issue in DP HPO encoder FIFO and result in blank CRCs. [How] Replace the immediate CRTC disable call with normal disable call Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Xi (Alex) Liu <xi.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Move dio files into dio folderBhuvanachandra Pinninti19-5/+37
[why] Refactor the code of dio to unit test. [how] Moved files to respective folders and changed cMakeLists and makefiles. Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Bhuvanachandra Pinninti <bpinnint@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Account for cursor prefetch BW in DML1 mode supportAlvin Lee1-0/+3
[Description] We need to ensure to take into account cursor prefetch BW in mode support or we may pass ModeQuery but fail an actual flip which will cause a hang. Flip may fail because the cursor_pre_bw is populated during mode programming (and mode programming is never called prior to ModeQuery). Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com> Reviewed-by: Nevenko Stupar <nevenko.stupar@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: fix a crash when clock source is reference for non otg ↵Wenjing Liu1-18/+20
master pipe [why] The function enumerates all pipes without checking pipe type. It is only supposed to call program pixel clock for OTG master pipe only. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Fix dmub timeout after fams2 enabledFangzhi Zuo1-1/+6
Reset fams stream count upon stream removal, otherwise fams2 state machine in dmub will get corrupted. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: un-block 8k with single dimmPaul Hsieh1-22/+0
[Why] Driver doesn't validate multi-display with scaling when OS calls DDI. This behavior causes the validated result to be a mismatch between some automated test cases. To address this issue, some workaround was added that caused issues in 8k. [How] Since the origin issue had been root caused, revert the previous workaround and unblock 8k with a single dimm. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Paul Hsieh <paul.hsieh@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Add available bandwidth calculation for audioRyan Seto2-6/+59
[Why] Audio for 8K 240Hz monitor was not available when it should be [How] Added calculation based on stream state Co-developed-by: Ryan Seto <ryanseto@amd.com> Reviewed-by: George Shen <george.shen@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Ryan Seto <ryanseto@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Cleanup dce_get_dp_ref_freq_khzDillon Varone1-1/+1
[WHY&HOW] Cleanup unnecessary code pathes as compile guards were added and removed overtime. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Check denominator crb_pipes before usedAlex Hung1-1/+1
[WHAT & HOW] A denominator cannot be 0, and is checked before used. This fixes 2 DIVIDE_BY_ZERO issues reported by Coverity. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Adjust cursor visibility between MPC slicesNevenko Stupar2-9/+39
[Why & How] When MPC enabled, need to adjust x and hot spot x position on one pipe when the cursor is between MPC slices i.e. when the cursor is moving from one MPC slice to next slice, while whole cursor size is not contained within one pipe, to make part of the cursor to be visible on the other pipe. Reviewed-by: Sridevi Arvindekar <sridevi.arvindekar@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Nevenko Stupar <nevenko.stupar@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Skip unnecessary abm disableSherry Wang1-0/+6
[Why] We try to disable abm immediately when it's being gradually disabled, which causes backlight ramping being paused in the middle [How] Don't disable abm immediately if abm has been or is being disabled through set_abm_level path Reviewed-by: Anthony Koo <anthony.koo@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Sherry Wang <yao.wang1@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Fix possible overflow in integer multiplicationAlex Hung11-22/+22
[WHAT & HOW] Integer multiplies integer may overflow in context that expects an expression of unsigned/siged long long (64 bits). This can be fixed by casting integer to unsigned/siged long long to force 64 bits results. This fixes 26 OVERFLOW_BEFORE_WIDEN issues reported by Coverity. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Add ASIC cap to limit DCC surface widthGeorge Shen3-0/+11
[Why] Certain configurations of DCN401 require ODM4:1 to support DCC for 10K surfaces. DCC should be conservatively disabled in those cases. The issue is that current logic limits 10K surface DCC for all configurations of DCN401. [How] Add DC ASIC cap to indicate max surface width that can support DCC. Disable DCC if this ASIC cap is non-zero and surface width exceeds it. Reviewed-by: Jun Lei <jun.lei@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Revert Add workaround to restrict max frac urgent for DPM0Teeger3-19/+0
This reverts commit 871512e36f9c1c2cb4e62eb860ca0438800e4d63 due to multiple issues found. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Teeger <gateeger@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Choose HUBP unbounded request based on DML outputSung Joon Kim1-10/+2
[why] Previously, we decide on the unbounded request purely based on pipe_cnt which is a wrong variable to use to determine how many pipes are in "use". DML already accounts for number of pipes in use along with other various factors and is a more reliable method of determination. [how] Use UnboundedRequestEnabledThisState to decide on unbounbded_req_enabled. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Sung Joon Kim <sungjoon.kim@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-07-01drm/amd/display: Fix divide by zero in CURSOR_DST_X_OFFSET calculationGeorge Shen1-2/+13
[Why] Certain situations cause pipes to have a recout of 0, such as when the dst_rect lies completely outside of a given ODM slice. [How] Skip calculation that transforms cursor coordinates to viewport space. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-28drm/amd/display: Fix null pointer deref in dcn20_resource.cAurabindo Pillai1-4/+5
Fixes a hang thats triggered when MPV is run on a DCN401 dGPU: mpv --hwdec=vaapi --vo=gpu --hwdec-codecs=all and then enabling fullscreen playback (double click on the video) The following calltrace will be seen: [ 181.843989] BUG: kernel NULL pointer dereference, address: 0000000000000000 [ 181.843997] #PF: supervisor instruction fetch in kernel mode [ 181.844003] #PF: error_code(0x0010) - not-present page [ 181.844009] PGD 0 P4D 0 [ 181.844020] Oops: 0010 [#1] PREEMPT SMP NOPTI [ 181.844028] CPU: 6 PID: 1892 Comm: gnome-shell Tainted: G W OE 6.5.0-41-generic #41~22.04.2-Ubuntu [ 181.844038] Hardware name: System manufacturer System Product Name/CROSSHAIR VI HERO, BIOS 6302 10/23/2018 [ 181.844044] RIP: 0010:0x0 [ 181.844079] Code: Unable to access opcode bytes at 0xffffffffffffffd6. [ 181.844084] RSP: 0018:ffffb593c2b8f7b0 EFLAGS: 00010246 [ 181.844093] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000004 [ 181.844099] RDX: ffffb593c2b8f804 RSI: ffffb593c2b8f7e0 RDI: ffff9e3c8e758400 [ 181.844105] RBP: ffffb593c2b8f7b8 R08: ffffb593c2b8f9c8 R09: ffffb593c2b8f96c [ 181.844110] R10: 0000000000000000 R11: 0000000000000000 R12: ffffb593c2b8f9c8 [ 181.844115] R13: 0000000000000001 R14: ffff9e3c88000000 R15: 0000000000000005 [ 181.844121] FS: 00007c6e323bb5c0(0000) GS:ffff9e3f85f80000(0000) knlGS:0000000000000000 [ 181.844128] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 181.844134] CR2: ffffffffffffffd6 CR3: 0000000140fbe000 CR4: 00000000003506e0 [ 181.844141] Call Trace: [ 181.844146] <TASK> [ 181.844153] ? show_regs+0x6d/0x80 [ 181.844167] ? __die+0x24/0x80 [ 181.844179] ? page_fault_oops+0x99/0x1b0 [ 181.844192] ? do_user_addr_fault+0x31d/0x6b0 [ 181.844204] ? exc_page_fault+0x83/0x1b0 [ 181.844216] ? asm_exc_page_fault+0x27/0x30 [ 181.844237] dcn20_get_dcc_compression_cap+0x23/0x30 [amdgpu] [ 181.845115] amdgpu_dm_plane_validate_dcc.constprop.0+0xe5/0x180 [amdgpu] [ 181.845985] amdgpu_dm_plane_fill_plane_buffer_attributes+0x300/0x580 [amdgpu] [ 181.846848] fill_dc_plane_info_and_addr+0x258/0x350 [amdgpu] [ 181.847734] fill_dc_plane_attributes+0x162/0x350 [amdgpu] [ 181.848748] dm_update_plane_state.constprop.0+0x4e3/0x6b0 [amdgpu] [ 181.849791] ? dm_update_plane_state.constprop.0+0x4e3/0x6b0 [amdgpu] [ 181.850840] amdgpu_dm_atomic_check+0xdfe/0x1760 [amdgpu] Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-28drm/amd/display: Add null check before access structsMa Ke1-0/+2
In enable_phantom_plane, we should better check null pointer before accessing various structs. Fixes: 09a4ec5da92c ("drm/amd/display: Refactor dc_state interface") Signed-off-by: Ma Ke <make24@iscas.ac.cn> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-28drm/amd/display: use swap() in is_config_schedulable()Jiapeng Chong1-7/+4
Use existing swap() function rather than duplicating its implementation. ./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c:1171:103-104: WARNING opportunity for swap(). ./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c:1231:99-100: WARNING opportunity for swap(). Reported-by: Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9400 Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-28drm/amd/display: Fix Makefile copyright noticesAlex Deucher4-29/+8
Leftover copy pasta from original code. Reviewed-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Harry.Wentland@amd.com
2024-06-28drm/amd/display: 3.2.290Aric Cyr1-1/+1
This version brings along the following: - Enable DCC on DCN401 - Add reg definitions for DCN401 DCC - Remove duplicate null check - Remove always true condition - Validate function returns - Ensure curve to hw translation succeed - Use periodic detection for ipx/headless - Fix 1DLUT setting for NL SDR blending - Adjust reg field for DSC wait for disconnect - Remove a redundant check in authenticated_dp - Add HW cursor visual confirm - Fix cursor issues with ODMs and magnification - Wait for double buffer update on ODM changes - Reset DSC memory status - Program CURSOR_DST_X_OFFSET in viewport space - Add null checks before accessing struct elements - Fix reduced resolution and refresh rate - Make DML2.1 P-State method force per stream - Add workaround to restrict max frac urgent for DPM0 - Call dpmm when checking mode support - resync OTG after DIO FIFO resync - Always enable HPO for DCN4 dGPU - Use sw cursor for DCN401 with rotation - Add Replay general cmd - Check HDCP returned status - Check and log for function error codes - Check and log for function error codes - Remove useless function call - Fix uninitialized variables in dcn401 - Fix cursor size issues - Run DC_LOG_DC after checking link->link_enc - Remove redundant checks for pipe_ctx->stream - Send DP_TOTAL_LTTPR_CNT during detection if LTTPR is present - Fix cursor issues with ODMs and HW rotations - Remove unnecessary variable - Remove redundant var from display_rq_dig_calc in dml - Refactor dccg401_get_other_enable_symclk_fe Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-28drm/amd/display: Enable DCC on DCN401Aurabindo Pillai22-2/+433
[WHAT] Add registers and entry points to enable DCC on DCN4x Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-28drm/amd/display: Remove always true conditionAlex Hung1-3/+1
[WHAT & HOW] advanced_pstate_switching was initialized to false and never assigned to another value; as a result !advanced_pstate_switching is always true and should be removed. This fixes 2 DEADCODE issues reported by Coverity. Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-28drm/amd/display: Validate function returnsAlex Hung3-5/+8
[WHAT & HOW] Function return values must be checked before data can be used in subsequent functions. This fixes 4 CHECKED_RETURN issues reported by Coverity. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-28drm/amd/display: Ensure curve to hw translation succeedAlex Hung2-4/+10
[WHAT & HOW] Check cm3_helper_translate_curve_to_hw_format runs successfully so the regamma_params is valid and can be used. Also revmoed two result assignments. This fixes 2 CHECKED_RETURN UNUSED_VALUE issues reported by Coverity. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-28drm/amd/display: Fix 1DLUT setting for NL SDR blendingRelja Vojvodic1-2/+2
[WHY] Enabling NL SDR blending caused the 1D LUTs to be set/populated in two different functions. This caused flickering as the LUT was set differently by the two functions, one of which should only have been modifying the 1D LUT if 3D LUT was enabled. [HOW] Added check to only modify the 1D LUT in populate_mcm if 3D LUT was enabled. Added blend_tf function update for non-main planes if the 3D LUT path was taken. Reviewed-by: Ilya Bakoulin <ilya.bakoulin@amd.co> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Relja Vojvodic <relja.vojvodic@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-28drm/amd/display: Adjust reg field for DSC wait for disconnectRyan Seto3-3/+6
[WHY] DSC was waiting for the wrong field to disconnect cleanly. [HOW] Changed field the DSC disconnect was waiting on. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Ryan Seto <ryanseto@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-28drm/amd/display: Add HW cursor visual confirmRyan Seto2-0/+30
[WHY] Added HW cursor visual confirm [HOW] Added visual confirm logic when programming cursor positions. HW is programmed on cursor updates since cursor can change without flips. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Ryan Seto <ryanseto@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-28drm/amd/display: Fix cursor issues with ODMs and magnificationNevenko Stupar1-0/+9
[WHY & HOW] Adjust hot spot positions between ODM slices when cursor magnification is used. Reviewed-by: Sridevi Arvindekar <sridevi.arvindekar@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Nevenko Stupar <nevenko.stupar@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-28drm/amd/display: Wait for double buffer update on ODM changesAlvin Lee7-1/+43
[WHAT & HOW] We must wait for ODM double buffer updates to complete before exiting the pipe update sequence or we may reduce DISPCLK and hit some transient underflow (pixel rate is reduced before the pipes have ODM enabled). Reviewed-by: Samson Tam <samson.tam@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-28drm/amd/display: Reset DSC memory statusDuncan Ma3-20/+71
[WHY] When system exits idle state followed by enabling the display, DSC memory may still be forced in a deep sleep or shutdown state. Intermittent DSC corruption is seen when display is visible. [HOW] When DSC is enabled, reset dsc memory to force and disable status. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Duncan Ma <duncan.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-28drm/amd/display: Program CURSOR_DST_X_OFFSET in viewport spaceAlvin Lee1-2/+10
[WHAT & HOW] According to register specifications, the CURSOR_DST_X_OFFSET is relative to the start of the data viewport, not RECOUT space. In this case we must transform the cursor coordinates passed to hubp401_cursor_set_position into viewport space to program this register. This fixes an underflow issue that occurs in scaled mode with low refresh rate. Reviewed-by: Nevenko Stupar <nevenko.stupar@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-28drm/amd/display: Add null checks before accessing struct elementsAlex Hung4-10/+16
[WHAT] 1. is_pwrseq0 needs to check link before accessing link->link_index. 2. context is checked before accessing its bw_ctx.dml2 3. clk_mgr_base->bw_params is checked before clk_table.num_entries_per_cl This fixes 4 REVERSE_INULL issues reported by Coverity. Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-28drm/amd/display: Fix reduced resolution and refresh rateDaniel Sa1-10/+11
[WHY] Some monitors are forced to a lower resolution and refresh rate after system restarts. [HOW] Some monitors may give invalid LTTPR information when queried such as indicating they have one DP lane instead of 4. If given an invalid DPCD version, skip over getting lttpr link rate and lane counts. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Daniel Sa <daniel.sa@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-28drm/amd/display: Make DML2.1 P-State method force per streamDillon Varone4-4/+5
[WHY & HOW] Currently the force only works for a single display, make it so it can be forced per stream. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-02 17:37:28 +0300