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path: root/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
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2023-11-28drm/amd/display: Change the DMCUB mailbox memory location from FB to inboxLewis Huang1-8/+14
commit 5911d02cac70d7fb52009fbd37423e63f8f6f9bc upstream. [WHY] Flush command sent to DMCUB spends more time for execution on a dGPU than on an APU. This causes cursor lag when using high refresh rate mouses. [HOW] 1. Change the DMCUB mailbox memory location from FB to inbox. 2. Only change windows memory to inbox. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Lewis Huang <lewis.huang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-07-25drm/amd/display: Add interface to modify DMUB panel power optionsPaul Hsieh1-0/+3
[Why] This option can vary depending on the panel and may be required to be called during sink detection phase before transmitter control. [How] Allow modify the bit depending on the eDP panel connected with a new interface. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Paul Hsieh <paul.hsieh@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-07-18drm/amd/display: Add helpers to get DMUB FW boot optionsCruise Hung1-0/+4
[Why & How] To query the bits and print them out for debug purposes. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alan Liu <haoping.liu@amd.com> Signed-off-by: Cruise Hung <cruise.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-30drm/amd/display: Set minimum requirement for using PSR-SU on RembrandtMario Limonciello1-0/+2
A number of parade TCONs are causing system hangs when utilized with older DMUB firmware and PSR-SU. Some changes have been introduced into DMUB firmware to add resilience against these failures. Don't allow running PSR-SU unless on the newer firmware. Cc: stable@vger.kernel.org Cc: Sean Wang <sean.ns.wang@amd.com> Cc: Marc Rossi <Marc.Rossi@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Cc: Tsung-hua (Ryan) Lin <Tsung-hua.Lin@amd.com> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2443 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-30drm/amd/display: Correct `DMUB_FW_VERSION` macroMario Limonciello1-1/+1
The `DMUB_FW_VERSION` macro has a mistake in that the revision field is off by one byte. The last byte is typically used for other purposes and not a revision. Cc: stable@vger.kernel.org Cc: Sean Wang <sean.ns.wang@amd.com> Cc: Marc Rossi <Marc.Rossi@amd.com> Cc: Hamza Mahfooz <Hamza.Mahfooz@amd.com> Cc: Tsung-hua (Ryan) Lin <Tsung-hua.Lin@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09Revert "drm/amd/display: cache trace buffer size"Leo Ma1-1/+0
Revert commit 257e9891db0b ("drm/amd/display: cache trace buffer size") to fix regression found in tests. Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Leo Ma <hanghong.ma@amd.com> Reviewed-by: Josip Pavic <Josip.Pavic@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-06-09drm/amd/display: cache trace buffer sizeJosip Pavic1-0/+1
[Why & How] Cache the trace buffer size retrieved from DMUB FW in the driver Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Josip Pavic <josip.pavic@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-25drm/amd/display: Add p-state debuggingSung Lee1-1/+2
[WHY] P-State related issues are fairly common but currently there is no way to debug these issues after the fact. [HOW] Add helpful registers to HW state queries Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Sung Lee <sunglee@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-25drm/amd/display: Restore rptr/wptr for DMCUB as workaroundJinZe.Xu1-0/+14
[Why] States may be desync after resume. [How] Sync sw state with hw state. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: JinZe.Xu <JinZe.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-04-18drm/amd/display: add mechanism to skip DCN initEric Yang1-1/+0
[Why] If optimized init is done in FW. DCN init can be skipped in driver. This need to be communicated between driver and fw and maintain backwards compatibility. [How] Use DMUB scratch 0 bit 2 to indicate optimized init done in fw and use DMUB scatch 4 bit 0 to indicate drive supports the optimized flow so FW will perform it. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-03-22drm/amd/display: Add CRC and DMUB test supportCharlene Liu1-0/+2
[Why & How] - Add CRC for test support - Add params to allow control into to DMUB. Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-01-13drm/amd/display: Update dmub header to match DMUBMustapha Ghaddar1-1/+15
[WHY] Last PR missed name of a struct to match in DMUB [HOW] Update the logic in dmub_cmh.h header Tested-by: Daniel Wheeler <Daniel.Wheeler@amd.com> Reviewed-by: Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Mustapha Ghaddar <mghaddar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-12-15drm/amd/display: Add DPIA NOTIFICATION logicMustapha Ghaddar1-0/+3
[WHY] Adding the new DPIA NOTIFY packets from DMUB As per the design with Cruise to account for 250ms response delay otherwise [HOW] Added th DPIA NOTIFY logic as per DMUB logic Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Mustapha Ghaddar <mghaddar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-10-11drm/amd/display: Display does not light up after S4 resumeMeenakshikumar Somasundaram1-0/+1
[Why] Dpia hpd interrupt processing is disabled when entering S4/S0i3 and would be reenabled after detection completes during resuming. Because, keeping hpd interrupts enabled during detection leads to multiple detections for the same hpd transition. There is a S4 case where dpia hpd interrupt is missed when driver is in transitioning from hpd interrupt processing disable to enable and the display does not light up. [How] - Added dmub inbox command DMUB_CMD__DPIA_HPD_INT_ENABLE to explicitly control dmub to issue dpia hpd interrupt or not. If dpia hpd interrupt is disabled, dmub will keep the hpd pending and post it once driver reenables dpia hpd interrupt or when querying with DMUB_CMD__QUERY_HPD_STATE. - Added dmub boot option dpia_hpd_int_enable_supported to notify dmub about whether DMUB_CMD__DPIA_HPD_INT_ENABLE command would be used. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Mustapha Ghaddar <Mustapha.Ghaddar@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-08-30drm/amd/display: Add support for visual confirm colorLeo (Hanghong) Ma1-0/+1
[Why] We want to get the visual confirm color of the bottom-most pipe for test automation. [How] Save the visual confirm color to plane_state before program to MPC; Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-14drm/amd/display: Add DCN314 version identifiersRoman Li1-0/+1
DCN 3.1.4 version and family ids Signed-off-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-03drm/amd/display: Add DMCUB source files and changes for DCN32/321Aurabindo Pillai1-0/+6
DMCUB is the display engine microcontroller which aids in modesetting and other display related features. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-03drm/amd/display: Add DCN32/321 version identifiersAurabindo Pillai1-0/+2
Add DCN3.2 asic identifiers. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-04drm/amd/display: Add Connection Manager boot option.Jimmy Kizito1-0/+1
[Why] Boot up behaviour may differ depending on the Connection Manager handling USB4 tunneling. [How] Send boot option to firmware to indicate Connection Manager. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-18drm/amd/display: Add DCN315 DMUBQingqing Zhuo1-0/+1
Add support for the DMUB firmware for DCN 3.1.5. Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-17drm/amd/display: Add DMUB support for DCN316Leo Li1-0/+1
Initialize DMUB for DCN316. Use same funcs as DCN31 for DCN316. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-22drm/amd/display: Only flush delta from last command executionNicholas Kazlauskas1-0/+1
[Why] We're currently flushing commands that had been previously been flushed or are currently being processed by the DMCUB when we don't immediately wait for idle after command execution. [How] Avoiding reflushing the data by keeping track of the last wptr. We'll treat this as the actual rptr by creating a copy of the inbox and modifying the copy's rptr. Reviewed-by: Eric Yang <Eric.Yang2@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-18drm/amd/display: Wait for ACK for INBOX0 HW LockAlvin Lee1-0/+41
[Why] In DC we want to wait for the INBOX0 HW Lock command to ACK before continuing. This is to ensure that the lock has been successfully acquired before programming HW in DC. [How] Add interfaces to send messages on INBOX0, poll for their completation and clear the ack. Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-11-03drm/amd/display: Added new DMUB boot option for power optimizationJake Wang1-0/+1
[Why] During Z10, root clock gating and memory low power registers needs to to be restored if optimization is enabled in driver. [How] Added new DMUB boot option for root clock gating and memory low power. Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Jake Wang <haonan.wang2@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-10-28drm/amd/display: Enable dpia in dmub only for DCN31 B0Jude Shih1-0/+1
[Why] DMUB binary is common for both A0 and B0. Hence, driver should notify FW about the support for DPIA in B0. [How] Added dpia_supported bit in dmub_fw_boot_options and will be set only for B0. Assign dpia_supported to true before dm_dmub_hw_init in B0 case. v2: fix build without CONFIG_DRM_AMD_DC_DCN (Alex) Signed-off-by: Jude Shih <shenshih@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-10-28drm/amd/display: Set phy_mux_sel bit in dmub scratch registerHansen1-0/+1
[Why] B0 has pipe mux for DIGC and DIGD which can be connected to PHYF/PHYG or PHYC/PHY D. [How] Based on chip internal hardware revision id determine it is B0 and set DMUB scratch register so DMUBFW can connect the display pipe is connected correctly to the dig. Cc: Wayne Lin <wayne.lin@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Hansen <Hansen.Dsouza@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-10-06drm/amd/display: Add dpia debug optionsMeenakshikumar Somasundaram1-0/+1
[Why & How] To add support for dpia debug options. Reviewed-by: Jimmy Kizito <Jimmy.Kizito@amd.com> Acked-by: Wayne Lin <Wayne.Lin@amd.com> Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-10-06drm/amd/display: Support for SET_CONFIG processing with DMUBMeenakshikumar Somasundaram1-0/+2
[Why] To process SET_CONFIG transactions with DMUB using inbox1 and outbox1 mail boxes. [How] 1) Added inbox1 DPIA command subtype DMUB_CMD__DPIA_SET_CONFIG_ACCESS to issue SET_CONFIG command to DMUB in dc_process_dmub_set_config_async(). DMUB processes the command with DPIA sends reply back immediately or in an outbox1 message triggering an outbox1 interrupt to driver. 2) DMUB posts SET_CONFIG reply as an Outbox1 message of type DMUB_OUT_CMD__SET_CONFIG_REPLY. 3) The dmub async to sync mechanism for AUX is modified to accommodate SET_CONFIG commands for both command issue and reply code paths. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Wayne Lin <Wayne.Lin@amd.com> Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-10-04drm/amd/display: Prevent using DMUB rptr that is out-of-boundsWyatt Wood1-0/+1
[Why] Running into bugchecks during stress test where rptr is 0xFFFFFFFF. Typically this is caused by a hard hang, and can come from HW outside of DCN. [How] To prevent bugchecks when writing the DMUB rptr, fist check that the rptr is valid. Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-09-14drm/amd/display: Add periodic detection when zstate is enabledEric Yang1-0/+4
[Why] When system is in Z10 HPD interrupts cannot fire, we may miss display configuration changes. [How] When Zstate is enabled, if DMUB indicate DCN has lost power, do a complete detection periodically. Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-08drm/amd/display: DMUB Outbound Interrupt Process-X86Chun-Liang Chang1-0/+18
[Why] dmub would notify x86 response time violation by GPINT_DATAOUT [How] 1. Use GPINT_DATAOUT to trigger x86 interrupt 2. Register GPINT_DATAOUT interrupt handler. 3. Trigger ACR while GPINT_DATAOUT occurred. Signed-off-by: Chun-Liang Chang <Chun-Liang.Chang@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-22drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCNAlex Deucher1-8/+0
No need for a separate flag now that DCN3.1 is not in bring up. Fold into DRM_AMD_DC_DCN like previous DCN IPs. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-16drm/amd/display: add DMUB registers to crash dump diagnostic data.Ashley Thomas1-0/+29
[WHY] Ability to triage DMCUB is improved with availability of certain dmub registers not currently captured in crash dump diagnostic data. [HOW] Add dmub registers to diagnostic data collection. Thanks Nicholas Kazlauskas for awesome input on this! Signed-off-by: Ashley Thomas <Ashley.Thomas2@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amd/display: Add DCN3.1 DMCUBNicholas Kazlauskas1-0/+12
DMCU-B (Display Micro-Controller Unit B) is a display microcontroller used for shared display functionality with BIOS and for advanced power saving display features. Extends the command header to include new DCN3.1 functionality. Adds new interfaces to DC dmub interface as well for z-state support. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-27drm/amd/display: Implement INBOX0 usage in driverAlvin Lee1-0/+1
[Why] Start using INBOX0 for HW Lock command [How] - Implement initial interface for INBOX0 HW lock message Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amd/display: Initial DC support for Beige GobyAurabindo Pillai1-0/+1
[Why&How] Add Beige Goby (DCN303) resource, irq service, & dmub loader. v2: fix nbio include (Alex) Signed-off-by: Chris Park <Chris.Park@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amd/display: Add get_current_time interface to dmub_srvWyatt Wood1-0/+1
[Why] Need to get current DMUB time. [How] Add get_current_time interface to dmub_srv. v2: drop whitespace changes (Alex) Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-11drm/amd/display: Extend DMUB HW params to allow DM to specify boot optionsEric Yang1-18/+19
[Why & How] Add the field to HW params to allow DM dynamically pass down debug and boot options as needed. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Wayne Lin <Wayne.Lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-24drm/amd/display: Fixed read/write pointer issue for get dmub traceYongqiang Sun1-1/+1
[Why] Driver get wrap around dmub trace data due to read pointer being increased incorrectly when there are multiple interrupt queues with very short interval [How] Check read/write pointer before copying data from ring buffer Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-02drm/amd/display: Implement dmub trace eventYongqiang Sun1-0/+14
[Why & How] DMUB FW send trace event via outbox0 interrupt. Driver will handle it. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-02drm/amd/display: Support for DMUB AUXMeenakshikumar Somasundaram1-0/+41
[WHY] To process AUX transactions with DMUB using inbox1 and outbox1 mail boxes. [HOW] 1) Added inbox1 command DMUB_CMD__DP_AUX_ACCESS to issue AUX commands to DMUB in dc_process_dmub_aux_transfer_async(). DMUB processes AUX cmd with DCN and sends reply back in an outbox1 message triggering an outbox1 interrupt to driver. 2) In existing driver implementation, AUX commands are processed synchronously by configuring DCN reg. But in DMUB AUX, driver sends an inbox1 message and waits for a conditional variable (CV) which will be signaled by outbox1 ISR. 3) As the driver holds dal and dc locks while waiting for CV, the outbox1 ISR is registered with noMutexWait set to true, which allows ISR to run and signal CV. This sets a constraint on ISR to not modify variables such as dc, dmub, etc. 4) Created dmub_outbox.c with dmub_enable_outbox_notification() to enable outbox1 mailbox. 5) New mailbox address ranges allocated for outbox1 of size DMUB_RB_SIZE. Created dmub functions for Outbox1: dmub_dcn20_setup_out_mailbox(), dmub_dcn20_get_outbox1_wptr() and dmub_dcn20_set_outbox1_rptr(). 6) Added functions dc_stat_get_dmub_notification() and dmub_srv_stat_get_notification() to retrieve Outbox1 message. 7) Currently, DMUB doesn't opens DDC in AUX mode before issuing AUX transaction. A workaround is added in dce_aux_transfer_dmub_raw() to open in DDC in AUX mode for every AUX transaction. 8) Added dc debug option enable_dmub_aux_for_legacy_ddc enable/disable DMUB AUX. This debug option is checked dce_aux_transfer_with_retries() to select the method to process AUX transactions. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-09drm/amd/display: Add support for runtime feature detection commandWyatt Wood1-0/+6
[Why] Add support for new fw command for runtime feature detection. [How] Driver sends command through ring buffer, and fw returns data back through this command. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-16drm/amd/display: Update dmub codeBhawanpreet Lakha1-1/+19
There is a delta in the dmub code - add boot options - add boot status - remove unused auto_load_is_done func pointer Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-05drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)Alex Deucher1-6/+0
Avoids confusion in configurations. v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled v3: rebase on latest code Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-12drm/amd/display: Add support for DCN302 (v2)Bhawanpreet Lakha1-0/+3
- add DCN302 resource, irq service, dmub loader, - handle DC_VERSION_DCN_3_02 - define DCN302 power gating functions - handle DCN302 in GPIO files - define I2C regs - add CONFIG_DRM_AMD_DC_DCN3_02 guard v2: rebase fixes (Alex) Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-05drm/amd/display: Add dcn3.01 support to DC (v2)Roman Li1-0/+3
Update dc for vangogh support. v2: fix compilation without DCN 301 set. Signed-off-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-11Revert "drm/amd/display: add mechanism to skip DCN init"Changfeng1-3/+2
To avoid s3 faild at the first cycle on renoir platform, it needs to revert this patch: drm/amd/display: add mechanism to skip DCN init Signed-off-by: changfeng <Changfeng.Zhu@amd.com> Ackedy-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: add mechanism to skip DCN initEric Yang1-2/+3
[Why] If optimized init is done in FW. DCN init be skipped in driver. This need to be communicated between driver and fw and maintain backwards compatibility. [How] Use DMUB scratch 0 bit 2 to indicate optimized init done in fw and use DMUB scatch 4 bit 0 to indicate drive supports the optimized flow so FW will perform it. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: runtime select dmub emulatior.Yongqiang Sun1-0/+4
[Why & How] Add emul specific hw function to dmub, in case of emulator is created, we can runtime switch between dmub emulator or dmub uC via is_virtual flag in dmub. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 DMUBBhawanpreet Lakha1-0/+3
DMUB (Display Micro-Controller Unit) Used to read/write regs Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-14 19:39:39 +0300