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path: root/drivers/gpu/drm/amd/include/asic_reg/dcn
AgeCommit message (Expand)AuthorFilesLines
2021-03-05drm/amd/amdgpu: Add missing BASE_IDX to dcn registerTom St Denis1-1/+1
2020-11-10drm/amdgpu: Add and use seperate reg headers for dcn302Bhawanpreet Lakha2-0/+78535
2020-10-05drm/amdgpu: add vangogh asic header files (v2)Huang Rui2-0/+66628
2020-08-24drm/amd/display: remove unintended executable modeLukas Bulwahn4-0/+0
2020-08-17drm/amd/display: Add DSC_DBG_EN shift/mask for dcn3Bhawanpreet Lakha1-0/+22
2020-06-03drm/amd/display: Add dcn30 Headers (v2)Jerry (Fangzhi) Zuo4-0/+92947
2020-01-16drm/amd/include: Add OCSC registersRodrigo Siqueira4-2/+24
2019-12-19drm/amdgpu: move dpcs headers to dpcs includesRoman Li2-3995/+0
2019-10-17drm/amd/display: Add DP_DPHY_INTERNAL_CTR regsBhawanpreet Lakha1-0/+10
2019-08-29drm/amd/display: Add Renoir registers (v3)Bhawanpreet Lakha4-0/+74495
2019-06-22drm/amd/display: Create DWB resource for DCN2Charlene Liu2-0/+20
2019-06-20drm/amdgpu: add DCN 2.0 register headersHawking Zhang2-0/+85539
2019-04-24drm/amd/include: Add HUBPREQ_DEBUG register offsetsLeo Li1-0/+8
2018-04-11drm/amdgpu: Add CM_TEST_DEBUG regs for DCNHarry Wentland2-3/+24
2018-02-19drm/amd/display: Adding missing TMZ sh/mask entries for DCN1 SURFACE_CONTROLHarry Wentland1-0/+14
2017-12-06drm/amd/include:cleanup raven1 dcn header files.Feifei Xu2-0/+68414