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path: root/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
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2021-04-09drm/amd/amdgpu: Add CP_IB1_BASE_* to gc_10_3_0 headersTom St Denis1-0/+6
2020-10-23drm/amdgpu: add GC 10.3 NOALLOC registersAlex Deucher1-0/+2
2020-09-18drm/amdgpu: add the GC 10.3 VRS registersAlex Deucher1-0/+4
2020-07-27drm/amd/amdgpu: Add RLC_CGTT_MGCG_OVERRIDE to gfx 10.3 headersTom St Denis1-0/+2
2020-07-01drm/amd/amdgpu: Fix offset for SQ_DEBUG_STS_GLOBAL on gfx10 (v2)Tom St Denis1-2/+2
2020-07-01drm/amd/amdgpu: Fix SQ_DEBUG_STS_GLOBAL* registersTom St Denis1-2/+4
2020-07-01drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bitsTom St Denis1-1/+2
2020-07-01drm/amd/amdgpu: Add SQ debug registers to GFX9/GFX10 headers (v2)Tom St Denis1-0/+1
2020-06-03drm/amdgpu: add GC 10.3 header files (v2)Likun Gao1-0/+13469