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path: root/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
AgeCommit message (Expand)AuthorFilesLines
2024-04-03drm/i915: Do not match JSL in ehl_combo_pll_div_frac_wa_needed()Jonathon Hall1-1/+1
2024-04-03drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLsVille Syrjälä1-4/+19
2024-04-03drm/i915: Include the PLL name in the debug messagesVille Syrjälä1-19/+20
2024-04-03drm/i915: Try to preserve the current shared_dpll for fastset on type-c portsVille Syrjälä1-1/+7
2024-04-03drm/i915: Replace a memset() with zero initializationVille Syrjälä1-3/+1
2023-11-24drm/i915: Stop printing pipe name as hexVille Syrjälä1-1/+1
2023-10-31drm/i915: Extract _intel_{enable,disable}_shared_dpll()Ville Syrjälä1-14/+23
2023-10-31drm/i915: Move the DPLL extra power domain handling up one levelVille Syrjälä1-6/+10
2023-10-31drm/i915: Abstract the extra JSL/EHL DPLL4 power domain betterVille Syrjälä1-22/+8
2023-10-31drm/i915: Use named initializers for DPLL infoVille Syrjälä1-63/+67
2023-10-06drm/i915: Simplify DPLL state checker calling conventionVille Syrjälä1-5/+9
2023-10-06drm/i915: Constify the crtc states in the DPLL checkerVille Syrjälä1-3/+3
2023-10-04drm/i915: s/dev_priv/i915/ in the shared_dpll codeVille Syrjälä1-440/+440
2023-10-04drm/i915: Introduce for_each_shared_dpll()Ville Syrjälä1-21/+17
2023-10-04drm/i915: Decouple I915_NUM_PLLS from PLL IDsVille Syrjälä1-2/+24
2023-10-04drm/i915: Stop requiring PLL index == PLL IDVille Syrjälä1-27/+36
2023-08-30Merge tag 'drm-next-2023-08-30' of git://anongit.freedesktop.org/drm/drmLinus Torvalds1-12/+17
2023-08-18drm/i915: Move abs_diff() to math.hAndy Shevchenko1-0/+1
2023-08-08drm/i915/adlp: s/ADLP/ALDERLAKE_P for display and graphics stepDnyaneshwar Bhadane1-1/+1
2023-08-08drm/i915/jsl: s/JSL/JASPERLAKE for platform/subplatform definesDnyaneshwar Bhadane1-10/+15
2023-08-08drm/i915/hsw: s/HSW/HASWELL for platform/subplatform definesDnyaneshwar Bhadane1-1/+1
2023-05-16drm/i915: Make the CRTC state consistent during sanitize-disablingImre Deak1-1/+1
2023-05-16drm/i915: Add helpers to reference/unreference a DPLL for a CRTCImre Deak1-12/+46
2023-05-15drm/i915/display: add i915 parameter to I915_STATE_WARN()Jani Nikula1-14/+16
2023-05-15drm/i915/dpll: drop a useless I915_STATE_WARN_ON()Jani Nikula1-2/+0
2023-04-14drm/i915/mtl: Add Support for C10 PHY message bus and pll programmingRadhakrishna Sripada1-1/+1
2023-02-16drm/i915/display/dpll: use intel_de_rmw if possibleAndrzej Hajda1-112/+53
2023-01-18drm/i915: move pch_ssc_use to display sub-struct under dpllJani Nikula1-2/+2
2022-11-17drm/i915/hti: abstract hti handlingJani Nikula1-9/+2
2022-11-11drm/i915: stop including i915_irq.h from i915_trace.hJani Nikula1-0/+1
2022-10-26drm/i915/tgl+: Sanitize DKL PHY register definitionsImre Deak1-24/+24
2022-10-26drm/i915/tgl+: Move DKL PHY register definitions to intel_dkl_phy_regs.hImre Deak1-0/+1
2022-10-26drm/i915: Rename intel_tc_phy_regs.h to intel_mg_phy_regs.hImre Deak1-1/+1
2022-10-26drm/i915/tgl+: Add locking around DKL PHY register accessesImre Deak1-32/+27
2022-09-26drm/i915: Nuke intel_get_shared_dpll_id()Ville Syrjälä1-22/+0
2022-09-26drm/i915: Always initialize dpll.lockVille Syrjälä1-1/+2
2022-09-26drm/i915: WARN if PLL ref/unref got messed upVille Syrjälä1-1/+6
2022-09-26drm/i915: Pimp DPLL ref/unref debugsVille Syrjälä1-3/+8
2022-09-26drm/i915: Drop pointless 'budget' variableVille Syrjälä1-16/+6
2022-09-08drm/i915: Set active dpll early for icl+Ville Syrjälä1-0/+6
2022-09-08drm/i915: Feed the DPLL output freq back into crtc_stateVille Syrjälä1-1/+23
2022-09-07drm/i915: Shuffle some PLL code aroundVille Syrjälä1-85/+85
2022-08-31drm/i915/dpll: replace BUG_ON() with drm_WARN_ON()Jani Nikula1-2/+4
2022-08-31drm/i915: move vbt to display.vbtJani Nikula1-9/+9
2022-08-31drm/i915: move and group cdclk under display.cdclkJani Nikula1-2/+2
2022-08-29drm/i915: move dpll under display.dpllJani Nikula1-56/+56
2022-06-28drm/i915: Fix error code in icl_compute_combo_phy_dpll()Dan Carpenter1-1/+1
2022-06-17drm/i915/dpll: move shared dpll state verification to intel_dpll_mgr.cJani Nikula1-0/+88
2022-06-16drm/i915: Implement w/a 22010492432 for adl-sVille Syrjälä1-2/+2
2022-05-31drm/i915: Clean up DPLL related debugsVille Syrjälä1-39/+9
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