Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2021-08-30 | drm/i915/dg2: UHBR tables added for pll programming | Animesh Manna | 1 | -0/+147 |
2021-08-26 | drm/i915/snps: constify struct intel_mpllb_state arrays harder | Jani Nikula | 1 | -7/+7 |
2021-08-13 | drm/i915/dg2: use existing mechanisms for SNPS PHY translations | Jani Nikula | 1 | -44/+17 |
2021-07-29 | drm/i915/dg2: Update lane disable power state during PSR | Gwan-gyeong Mun | 1 | -0/+14 |
2021-07-29 | drm/i915/dg2: Wait for SNPS PHY calibration during display init | Matt Roper | 1 | -0/+15 |
2021-07-29 | drm/i915/dg2: Add vswing programming for SNPS phys | Matt Roper | 1 | -0/+54 |
2021-07-29 | drm/i915/dg2: Add MPLLB programming for HDMI | Matt Roper | 1 | -12/+274 |
2021-07-29 | drm/i915/dg2: Add MPLLB programming for SNPS PHY | Matt Roper | 1 | -0/+517 |