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path: root/drivers/gpu/drm/i915/display/intel_vrr.c
AgeCommit message (Expand)AuthorFilesLines
2024-08-23drm/i915/vrr: convert to struct intel_displayJani Nikula1-66/+61
2024-07-09drm/i915/display: Cache adpative sync caps to use it laterMitul Golani1-2/+1
2024-06-24drm/i915/display: Consider adjusted_pixel_rate to be u64Mitul Golani1-1/+1
2024-06-17drm/i915/display: Update calculation to avoid overflowMitul Golani1-4/+5
2024-06-13drm/i915/display: Send vrr vsync params whne vrr is enabledMitul Golani1-1/+2
2024-06-12drm/i915: Rename all bigjoiner to joinerStanislav Lisovskiy1-1/+1
2024-06-11drm/i915: Compute CMRR and calculate vtotalMitul Golani1-11/+81
2024-06-11drm/i915/display: Compute vrr vsync paramsMitul Golani1-8/+9
2024-06-11drm/i915: Update trans_vrr_ctl flag when cmrr is computedMitul Golani1-2/+8
2024-06-11drm/i915: Define and compute Transcoder CMRR registersMitul Golani1-0/+20
2024-06-11drm/i915: Separate VRR related register definitionsMitul Golani1-0/+1
2024-05-10drm/i915: pass dev_priv explicitly to TRANS_VRR_VSYNCJani Nikula1-3/+6
2024-05-10drm/i915: pass dev_priv explicitly to TRANS_PUSHJani Nikula1-4/+5
2024-05-10drm/i915: pass dev_priv explicitly to TRANS_VRR_FLIPLINEJani Nikula1-2/+4
2024-05-10drm/i915: pass dev_priv explicitly to TRANS_VRR_STATUSJani Nikula1-1/+2
2024-05-10drm/i915: pass dev_priv explicitly to TRANS_VRR_VMINJani Nikula1-2/+4
2024-05-10drm/i915: pass dev_priv explicitly to TRANS_VRR_VMAXJani Nikula1-2/+4
2024-05-10drm/i915: pass dev_priv explicitly to TRANS_VRR_CTLJani Nikula1-5/+8
2024-04-08drm/i915/vrr: Disable VRR when using bigjoinerVille Syrjälä1-0/+7
2024-04-04drm/i915/display: Compute vrr_vsync paramsMitul Golani1-2/+31
2024-03-07drm/i915/vrr: Generate VRR "safe window" for DSBVille Syrjälä1-3/+4
2023-09-20drm/i915: Implement transcoder LRR for TGL+Ville Syrjälä1-1/+6
2023-09-20drm/i915: Validate that the timings are within the VRR rangeVille Syrjälä1-2/+2
2023-09-20drm/i915: Relocate is_in_vrr_range()Ville Syrjälä1-0/+9
2023-04-12drm/i915/vrr: Relocate VRR enable/disableVille Syrjälä1-19/+29
2023-04-12drm/i915/vrr: Make delayed vblank operational in VRR mode on adl/dg2Ville Syrjälä1-0/+8
2023-04-12drm/i915/vrr: Eliminate redundant function argumentsVille Syrjälä1-6/+4
2023-03-01drm/i915/vrr: Fix "window2" handlingVille Syrjälä1-8/+2
2022-12-08drm/i915/vrr: Be more careful with the bits in TRANS_VRR_CTLVille Syrjälä1-13/+23
2022-12-08drm/i915/vrr: Fix guardband/vblank exit length calculation for adl+Ville Syrjälä1-3/+3
2022-12-08drm/i915/vrr: Make registers latch in a consitent place on icl/tglVille Syrjälä1-11/+2
2022-11-11drm/i915: stop including i915_irq.h from i915_trace.hJani Nikula1-0/+1
2022-08-29drm/i915/vrr: drop window2_delay member from i915Jani Nikula1-4/+10
2022-06-01drm/i915: Parse VRR capability from VBTVille Syrjälä1-6/+16
2022-05-27drm/i915: Pass intel_connector to intel_vrr_is_capable()Ville Syrjälä1-7/+7
2022-03-04drm/i915: Move framestart_delay to crtc_stateVille Syrjälä1-2/+2
2021-11-18drm/i915: Fix framestart_delay commens in VRR codeVille Syrjälä1-3/+3
2021-11-18drm/i915: Do vblank evasion correctly if vrr push has already been sentVille Syrjälä1-0/+12
2021-05-26drm/i915/xelpd: Add VRR guardband for VRR CTLManasi Navare1-17/+41
2021-05-05drm/i915: Don't include intel_de.h from intel_display_types.hVille Syrjälä1-0/+1
2021-01-26drm/i915: Fix vblank timestamps with VRRVille Syrjälä1-0/+4
2021-01-26drm/i915/display: Helpers for VRR vblank min and max startVille Syrjälä1-0/+36
2021-01-26drm/i915/display: Add HW state readout for VRRManasi Navare1-0/+20
2021-01-26drm/i915/display/vrr: Disable VRR in modeset disable pathManasi Navare1-0/+13
2021-01-26drm/i915/display/vrr: Send VRR push to flip the frameManasi Navare1-0/+13
2021-01-26drm/i915/display/vrr: Configure and enable VRR in modeset enableManasi Navare1-0/+22
2021-01-26drm/i915/display/dp: Compute VRR state in atomic_checkManasi Navare1-0/+70
2021-01-26drm/i915/display/dp: Attach and set drm connector VRR propertyAditya Swarup1-2/+2
2021-01-26drm/i915/display/vrr: Create VRR file and add VRR capability checkManasi Navare1-0/+31
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-28 11:08:36 +0300