summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2015-06-29drm/i915: Make sample_c messages go faster on Haswell.Kenneth Graunke1-0/+1
2015-05-18drm/i915: cope with large i2c transfersDmitry Torokhov1-0/+1
2015-01-27drm/i915: Disable PSMI sleep messages on all rings around context switchesChris Wilson1-0/+2
2015-01-27drm/i915: Invalidate media caches on gen7Chris Wilson1-0/+1
2015-01-27drm/i915: save/restore GMBUS freq across suspend/resume on gen4Jesse Barnes1-0/+1
2014-10-01drm/i915: Enable pixel replicated modes on BDW and HSW.Clint Taylor1-0/+3
2014-09-29Revert "drm/i915/bdw: BDW Software Turbo"Daniel Vetter1-4/+0
2014-09-19drm/i915: Extend BIOS stolen mem handling to all platformDaniel Vetter1-0/+8
2014-09-16Merge tag 'drm-intel-next-2014-09-05' of git://anongit.freedesktop.org/drm-in...Dave Airlie1-17/+18
2014-09-16drm: backmerge tag 'v3.17-rc5' into drm-nextDave Airlie1-4/+8
2014-09-08drm/i915: Evict CS TLBs between batchesChris Wilson1-4/+8
2014-09-03drm/i915: Idle unused rings on gen2/3 during init/resumeVille Syrjälä1-0/+7
2014-09-03drm/i915: Disable trickle feed for gen2/3Ville Syrjälä1-0/+4
2014-09-03drm/i915/bdw: BDW Software TurboDaisy Sun1-0/+4
2014-09-03drm/i915: Populate mem_freq in init_gt_powerwave()Ville Syrjälä1-6/+0
2014-09-03drm/i915: Rename defines for selection of ddi buffer translation slotSonika Jindal1-9/+1
2014-09-03drm/i915: Parametrize PANEL_PORT_SELECT_VLVVille Syrjälä1-2/+1
2014-09-03drm/i915: Add 180 degree primary plane rotation supportSonika Jindal1-0/+1
2014-08-13drm/i915: Add support for variable cursor size on 845/865Ville Syrjälä1-1/+2
2014-08-12drm/i915/bdw: Interrupts with logical ringsOscar Mateo1-0/+2
2014-08-12drm/i915/bdw: GEN-specific logical ring emit requestOscar Mateo1-0/+1
2014-08-11drm/i915/bdw: Populate LR contexts (somewhat)Oscar Mateo1-0/+1
2014-08-08drm/i915: Add sprite watermark programming for VLV and CHVGajanan Bhat1-6/+3
2014-08-08drm/i915: Generalize drain latency computationGajanan Bhat1-0/+1
2014-08-08drm/i915: Polish the chv cmnlane resrt macrosVille Syrjälä1-5/+2
2014-08-08drm/i915: Parametrize VLV_DDL registersVille Syrjälä1-41/+13
2014-08-08drm/i915: Fill out the FWx watermark register definesVille Syrjälä1-15/+123
2014-08-08drm/i915: Add 180 degree sprite rotation supportVille Syrjälä1-0/+3
2014-08-08drm/i915: remove duplicate register definesPaulo Zanoni1-2/+0
2014-08-08drm/i915: Introduce FBC False Color for debug purposes.Rodrigo Vivi1-0/+1
2014-08-08drm/i915: Clarify CHV swing margin/deemph bitsVille Syrjälä1-2/+6
2014-08-08drm/i915: Add cdclk change support for chvVille Syrjälä1-0/+4
2014-08-08drm/i915: Add DP training pattern 3 for CHVVille Syrjälä1-0/+2
2014-08-08drm/i915: Add chv port D TX wellsVille Syrjälä1-0/+4
2014-08-08drm/i915: Add per-pipe power wells for chvVille Syrjälä1-0/+12
2014-08-08drm/i915: Add chv cmnlane power wellsVille Syrjälä1-0/+1
2014-08-07drm/i915: Fix drain latency precision multipler for VLVZhenyu Wang1-25/+25
2014-08-05Merge tag 'v3.16' into drm-nextDave Airlie1-0/+3
2014-07-29Merge remote-tracking branch 'airlied/drm-next' into drm-intel-nextDaniel Vetter1-2/+9
2014-07-21drm/i915: add some registers need for displayport MST support.Dave Airlie1-2/+9
2014-07-12drm/i915/chv: calculate rc6 residency correctlyMika Kuoppala1-1/+1
2014-07-11drm/i915: populate mem_freq/cz_clock for chvDeepak S1-0/+6
2014-07-11drm/i915: Switch to common shared dpll framework for WRPLLsDaniel Vetter1-0/+1
2014-07-11drm/i915: State readout support for WRPLLsDaniel Vetter1-0/+1
2014-07-11drm/i915: State readout and cross-checking for ddi_pll_selDaniel Vetter1-0/+1
2014-07-11drm/i915: Clean up WRPLL/SPLL #definesDaniel Vetter1-3/+4
2014-07-10drm/i915: fix D_COMP usage on BDWPaulo Zanoni1-1/+4
2014-07-09drm/i915: Don't clobber the GTT when it's within stolen memoryVille Syrjälä1-0/+3
2014-07-08drm/i915/vlv: WA for Turbo and RC6 to work together.Deepak S1-0/+11
2014-07-08drm/i915/bdw: implement semaphore waitBen Widawsky1-0/+3
generated by cgit v1.2.3 (git 2.39.0) at 2024-10-19 07:21:04 +0300