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path: root/drivers/gpu/drm/i915/i915_reg.h
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2022-03-25Merge tag 'drm-next-2022-03-24' of git://anongit.freedesktop.org/drm/drmLinus Torvalds1-4737/+569
2022-03-07drm/i915/psr: Set "SF Partial Frame Enable" also on full updateJouni Högander1-0/+1
2022-03-02drm/i915/xehp: Define compute class and engineMatt Roper1-0/+4
2022-02-25Merge drm/drm-next into drm-intel-gt-nextTvrtko Ursulin1-4737/+559
2022-02-23Merge tag 'drm-intel-gt-next-2022-02-17' of git://anongit.freedesktop.org/drm...Rodrigo Vivi1-0/+4
2022-02-23drm/i915/tgl: Simply subplatform detectionJosé Roberto de Souza1-6/+0
2022-02-21drm/i915/adlp: Add TypeC PHY TBT->DP-alt/legacy mode switch workaroundImre Deak1-0/+6
2022-02-21drm/i915/reg: split out icl_dsi_regs.hJani Nikula1-333/+0
2022-02-21drm/i915/reg: split out vlv_dsi_regs.h and vlv_dsi_pll_regs.hJani Nikula1-574/+0
2022-02-21drm/i915/dsi: add separate init timer mask definition for ICL DSIJani Nikula1-0/+1
2022-02-20drm/i915/lmem: Enable lmem for platforms with Flat CCSAbdiel Janulgue1-0/+3
2022-02-19drm/i915/dg2: Enable 5th portMatt Roper1-0/+1
2022-02-19drm/i915: Fix for PHY_MISC_TC1 offsetJouni Högander1-2/+4
2022-02-18drm/i915/display: Implement Wa_16013835468José Roberto de Souza1-5/+8
2022-02-18drm/i915/display/tgl+: Implement new PLL programming stepJosé Roberto de Souza1-0/+12
2022-02-18drm/i915: Polish ilk+ wm register bitsVille Syrjälä1-21/+20
2022-02-18drm/i915: Clean up SSKPD/MLTR definesVille Syrjälä1-8/+0
2022-02-16drm/i915: Move MCHBAR registers to their own headerMatt Roper1-203/+0
2022-02-16drm/i915: Define MCH registers relative to MCHBAR_MIRROR_BASEMatt Roper1-6/+6
2022-02-15drm/i915/dg1: Update DMC_DEBUG3 registerChuansheng Liu1-1/+2
2022-02-11drm/i915/dg2: Add Wa_22011450934Ramalingam C1-0/+4
2022-02-03Merge drm/drm-next into drm-intel-gt-nextJoonas Lahtinen1-2/+17
2022-02-02drm/i915: Move [more] GT registers to their own header fileMatt Roper1-125/+0
2022-02-02drm/i915: Only include i915_reg.h from .c filesMatt Roper1-3/+0
2022-02-02drm/i915: Move GT registers to their own header fileMatt Roper1-1426/+0
2022-02-02drm/i915: Parameterize MI_PREDICATE registersMatt Roper1-10/+1
2022-02-02drm/i915: Parameterize R_PWR_CLK_STATE register definitionMatt Roper1-15/+0
2022-02-02drm/i915/perf: Move OA regs to their own headerMatt Roper1-485/+0
2022-02-02drm/i915: remove VGA register definitionsJani Nikula1-41/+0
2022-01-31Merge drm/drm-next into drm-intel-nextRodrigo Vivi1-16/+155
2022-01-31drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for referenceUmesh Nerlige Ramappa1-1/+2
2022-01-28drm/i915/dg2: Add Wa_14015227452Matt Roper1-0/+1
2022-01-28drm/i915: Clean up M/N register definesVille Syrjälä1-19/+3
2022-01-26drm/i915: Clean up PIPESRC definesVille Syrjälä1-0/+4
2022-01-26drm/i915: Clean up PCH_TRANSCONF/TRANS_DP_CTL bit definesVille Syrjälä1-32/+26
2022-01-26drm/i915: Clean up PIPECONF bit definesVille Syrjälä1-56/+52
2022-01-26drm/i915: Clean up SKL_BOTTOM_COLOR definesVille Syrjälä1-2/+2
2022-01-26drm/i915: Clean up PIPEMISC register definesVille Syrjälä1-16/+19
2022-01-26drm/i915: Bump DSL linemask to 20 bitsVille Syrjälä1-2/+2
2022-01-26drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for referenceUmesh Nerlige Ramappa1-1/+2
2022-01-25drm/i915: Flush TLBs before releasing backing storeTvrtko Ursulin1-0/+11
2022-01-24drm/i915/dg2: Add Wa_18018781329Matt Roper1-0/+4
2022-01-24drm/i915: Clean up pre-skl primary plane registersVille Syrjälä1-46/+62
2022-01-20drm/i915: Clean up vlv/chv sprite plane registersVille Syrjälä1-38/+65
2022-01-18drm/i915: Clean up cursor registersVille Syrjälä1-32/+39
2022-01-18drm/i915: Clean up g4x+ sprite plane registersVille Syrjälä1-28/+45
2022-01-18drm/i915: Clean up ivb+ sprite plane registersVille Syrjälä1-32/+49
2022-01-18drm/i915: Use REG_BIT() & co. for universal plane bitsVille Syrjälä1-87/+110
2022-01-18drm/i915: Sipmplify PLANE_STRIDE maskingVille Syrjälä1-2/+1
2022-01-17drm/i915/display/adlp: Implement new step in the TC voltage swing prog sequenceJosé Roberto de Souza1-2/+6
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