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path: root/drivers/gpu/drm/i915/intel_lrc.c
AgeCommit message (Expand)AuthorFilesLines
2016-01-29drm/i915: Make sure DC writes are coherent on flush.Francisco Jerez1-0/+1
2015-12-11drm/i915: mark GEM object pages dirty when mapped & written by the CPUDave Gordon1-7/+4
2015-12-10drm/i915: intel_ring_initialized() must be simple and inlineDave Gordon1-5/+12
2015-12-04Revert "drm/i915: Extend LRC pinning to cover GPU context writeback"Daniel Vetter1-113/+23
2015-12-03drm/i915: Extend LRC pinning to cover GPU context writebackNick Hoath1-23/+113
2015-11-23Merge tag 'v4.4-rc2' into drm-intel-next-queuedDaniel Vetter1-7/+33
2015-11-19Revert "drm/i915: Initialize HWS page address after GPU reset"Arun Siluvery1-6/+0
2015-11-18drm/i915: Type safe register read/writeVille Syrjälä1-2/+2
2015-11-18drm/i915: Wrap context LRI init in a macroVille Syrjälä1-51/+40
2015-11-18drm/i915: Give names to more ring registersVille Syrjälä1-11/+11
2015-11-18drm/i915: Wrap ASSIGN_CTX_{PDP,PM4L} in do {} while(0)Ville Syrjälä1-4/+4
2015-11-18drm/i915: Add wa_ctx_emit_reg()Ville Syrjälä1-4/+6
2015-11-18drm/i915: Add functions to emit register offsets to the ringVille Syrjälä1-4/+4
2015-11-10Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds1-181/+246
2015-10-29drm/i915: make A0 wa's applied to A1Tim Gore1-4/+4
2015-10-28drm/i915: Recover all available ringbuffer space following resetChris Wilson1-0/+1
2015-10-21drm/i915: add helpers for platform specific revision id range checksJani Nikula1-13/+13
2015-10-21drm/i915/bxt: add revision id for A1 stepping and use itJani Nikula1-4/+4
2015-10-20Merge tag 'drm-intel-next-2015-10-10' of git://anongit.freedesktop.org/drm-in...Dave Airlie1-15/+0
2015-10-16Merge commit '06d1ee32a4d25356a710b49d5e95dbdd68bdf505' of git://git.kernel.o...Dave Airlie1-7/+32
2015-10-13drm/i915: Flush pipecontrol post-sync writesChris Wilson1-0/+1
2015-10-07drm/i915: Kill DRI1 cliprectsChris Wilson1-15/+0
2015-09-28drm/i915: Consider HW CSB write pointer before resetting the sw read pointerMichel Thierry1-7/+32
2015-09-23drm/i915: Remove extraneous request cancel.Nick Hoath1-1/+0
2015-09-23drm/i915: Parametrize LRC registersVille Syrjälä1-5/+3
2015-09-22drm/i915: fix handling gen8_emit_flush_coherentl3_wa resultAndrzej Hajda1-3/+4
2015-09-14drm/i915: Fix warnings while make xmldocs caused by intel_lrc.cMasanari Iida1-2/+1
2015-09-14drm/i915: Split alloc from init for lrcNick Hoath1-84/+80
2015-09-14drm/i915/lrc: Prevent preemption when lite-restore is disabledMichel Thierry1-6/+18
2015-09-14drm/i915: WaEnableForceRestoreInCtxtDescForVCS is for video engines onlyMichel Thierry1-4/+4
2015-09-04drm/i915: Refactor common ringbuffer allocation codeChris Wilson1-37/+12
2015-09-02Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queuedDaniel Vetter1-0/+2
2015-09-02drm/i915: Always enable execlists on BDW for vgpuZhiyuan Lv1-0/+6
2015-09-02drm/i915: preallocate pdps for 32 bit vgpuZhiyuan Lv1-1/+2
2015-08-26drm/i915/bxt: work around HW coherency issue when accessing GPU seqnoImre Deak1-8/+56
2015-08-26drm/i915: Change SRM, LRM instructions to use correct lengthArun Siluvery1-2/+2
2015-08-24Merge tag 'v4.2-rc8' into drm-nextDave Airlie1-0/+2
2015-08-17drm/i915: Flag the execlists context object as dirty after every useChris Wilson1-0/+2
2015-08-14drm/i915: Integrate GuC-based command submissionAlex Dai1-17/+38
2015-08-14drm/i915: Expose one LRC function for GuC submission modeDave Gordon1-5/+5
2015-08-14drm/i915/gen8: Add 4 level switching infrastructure and lrc supportMichel Thierry1-18/+42
2015-08-14drm/i915: Check idle to active before processing CSQMika Kuoppala1-0/+3
2015-08-14drm/i915: Use masked write for Context Status Buffer PointerMika Kuoppala1-1/+1
2015-07-21drm/i915: Add provision to extend Golden context batchArun Siluvery1-0/+6
2015-07-15Merge tag 'drm-intel-fixes-2015-07-15' into drm-intel-next-queuedDaniel Vetter1-0/+6
2015-07-15drm/i915/gen9: Add WaSetDisablePixMaskCammingAndRhwoInCommonSliceChickenArun Siluvery1-0/+10
2015-07-15drm/i915/gen9: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaroundArun Siluvery1-0/+16
2015-07-15drm/i915/gen9: Add WaDisableCtxRestoreArbitration workaroundArun Siluvery1-2/+11
2015-07-15drm/i915: Enable WA batch buffers for Gen9Arun Siluvery1-3/+47
2015-07-14drm/i915: Added Programming of the MOCSPeter Antoine1-2/+10
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