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path: root/drivers/gpu/drm/msm/disp
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2024-04-23drm/msm: convert msm_format::unpack_align_msb to the flagDmitry Baryshkov4-14/+6
Instead of having a u8 or bool field unpack_align_msb, convert it to the flag, this save space in the tables and allows us to handle all booleans in the same way. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/590427/ Link: https://lore.kernel.org/r/20240420-dpu-format-v2-7-9e93226cbffd@linaro.org
2024-04-23drm/msm: convert msm_format::unpack_tight to the flagDmitry Baryshkov7-47/+41
Instead of having a u8 or bool field unpack_tight, convert it to the flag, this save space in the tables and allows us to handle all booleans in the same way. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/590428/ Link: https://lore.kernel.org/r/20240420-dpu-format-v2-6-9e93226cbffd@linaro.org
2024-04-23drm/msm: merge dpu_format and mdp_format in struct msm_formatDmitry Baryshkov28-304/+295
Structures dpu_format and mdp_format are largely the same structures. In order to remove duplication between format databases, merge these two stucture definitions into the global struct msm_format. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/590434/ Link: https://lore.kernel.org/r/20240420-dpu-format-v2-5-9e93226cbffd@linaro.org
2024-04-23drm/msm/dpu: pull format flag definitions to mdp_format.hDmitry Baryshkov8-85/+109
In preparation to merger of formats databases, pull format flag definitions to mdp_format.h header, so that they are visibile to both dpu and mdp drivers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/590425/ Link: https://lore.kernel.org/r/20240420-dpu-format-v2-4-9e93226cbffd@linaro.org
2024-04-23drm/msm/dpu: in dpu_format replace bitmap with unsigned long fieldDmitry Baryshkov2-18/+16
Using bitmap for the flags results in a clumsy syntax on test_bit, replace it with unsigned long type and simple binary ops. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/590422/ Link: https://lore.kernel.org/r/20240420-dpu-format-v2-3-9e93226cbffd@linaro.org
2024-04-23drm/msm: add arrays listing formats supported by MDP4/MDP5 hardwareDmitry Baryshkov4-42/+80
MDP4 and MDP5 drivers enumerate supported formats each time the plane is created. In preparation to merger of MDP DPU format databases, define precise formats list, so that changes to the database do not cause the driver to add unsupported format to the list. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/590421/ Link: https://lore.kernel.org/r/20240420-dpu-format-v2-2-9e93226cbffd@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-04-22drm/msm/dpu: use format-related definitions from mdp_common.xml.hDmitry Baryshkov8-219/+169
Instead of having DPU-specific defines, switch to the definitions from the mdp_common.xml.h file. This is the preparation for merged of DPU and MDP format tables. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/590420/ Link: https://lore.kernel.org/r/20240420-dpu-format-v2-1-9e93226cbffd@linaro.org
2024-04-22drm/msm/dpu: Rename `ctx` parameter to `intf` to match other functionsMarijn Suijten1-7/+7
All other functions in dpu_hw_intf name the "self" parameter `intf`, except dpu_hw_intf_setup_timing_engine() and the recently added dpu_hw_intf_program_intf_cmd_cfg(). Clean that up for consistency. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/589903/ Link: https://lore.kernel.org/r/20240417-drm-msm-initial-dualpipe-dsc-fixes-v1-7-78ae3ee9a697@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-04-22drm/msm/dpu: Allow configuring multiple active DSC blocksMarijn Suijten1-3/+6
Just like the active interface and writeback block in ctl_intf_cfg_v1(), and later the rest of the blocks in followup active-CTL fixes or reworks, multiple calls to this function should enable additional DSC blocks instead of overwriting the blocks that are enabled. This pattern is observed in an active-CTL scenario since DPU 5.0.0 where for example bonded-DSI uses a single CTL to drive multiple INTFs, and each encoder calls this function individually with the INTF (hence the pre-existing update instead of overwrite of this bitmask) and DSC blocks it wishes to be enabled, and expects them to be OR'd into the bitmask. The reverse already exists in reset_intf_cfg_v1() where only specified DSC blocks are removed out of the CTL_DSC_ACTIVE bitmask (same for all other blocks and ACTIVE bitmasks), leaving the rest enabled. Fixes: 77f6da90487c ("drm/msm/disp/dpu1: Add DSC support in hw_ctl") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/589902/ Link: https://lore.kernel.org/r/20240417-drm-msm-initial-dualpipe-dsc-fixes-v1-4-78ae3ee9a697@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-04-22drm/msm/dpu: Always flush the slave INTF on the CTLMarijn Suijten1-3/+0
As we can clearly see in a downstream kernel [1], flushing the slave INTF is skipped /only if/ the PPSPLIT topology is active. However, when DPU was originally submitted to mainline PPSPLIT was no longer part of it (seems to have been ripped out before submission), but this clause was incorrectly ported from the original SDE driver. Given that there is no support for PPSPLIT (currently), flushing the slave INTF should /never/ be skipped (as the `if (ppsplit && !master) goto skip;` clause downstream never becomes true). [1]: https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers/-/blob/display-kernel.lnx.5.4.r1-rel/msm/sde/sde_encoder_phys_cmd.c?ref_type=heads#L1131-1139 Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/589901/ Link: https://lore.kernel.org/r/20240417-drm-msm-initial-dualpipe-dsc-fixes-v1-3-78ae3ee9a697@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-04-22drm/msm: Drop msm_read/writelKonrad Dybcio2-4/+4
Totally useless. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Andrew Halaney <ahalaney@redhat.com> Patchwork: https://patchwork.freedesktop.org/patch/588804/ Link: https://lore.kernel.org/r/20240410-topic-msm_rw-v1-1-e1fede9ffaba@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-04-22drm/msm: drop display-related headersDmitry Baryshkov3-3271/+0
Now as the headers are generated during the build step, drop pre-generated copies of the display-related headers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/585860/ Link: https://lore.kernel.org/r/20240401-fd-xml-shipped-v5-12-4bdb277a85a1@linaro.org
2024-04-22drm/msm/mdp5: add writeback block basesDmitry Baryshkov1-0/+11
In order to stop patching the mdp5 headers, import definitions for the writeback blocks. This part is extracted from the old Rob's patch. Co-developed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/585842/ Link: https://lore.kernel.org/r/20240401-fd-xml-shipped-v5-1-4bdb277a85a1@linaro.org
2024-04-22drm/msm: convert all pixel format logging to use %p4ccJani Nikula4-19/+19
Logging u32 pixel formats using %4.4s format string with a pointer to the u32 is somewhat questionable, as well as dependent on byte order. There's a kernel extension format specifier %p4cc to format 4cc codes. Use it across the board in msm for pixel format logging. This should also fix the reported build warning: include/drm/drm_print.h:536:35: warning: '%4.4s' directive argument is null [-Wformat-overflow=] Reported-by: Aishwarya TCV <aishwarya.tcv@arm.com> Closes: https://lore.kernel.org/r/2ac758ce-a196-4e89-a397-488ba31014c4@arm.com Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Aishwarya TCV <aishwarya.tcv@arm.com> Patchwork: https://patchwork.freedesktop.org/patch/587758/ Link: https://lore.kernel.org/r/20240405092907.2334007-1-jani.nikula@intel.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-04-08drm/msm/dpu: add current resource allocation to dumped stateDmitry Baryshkov4-0/+78
Provide atomic_print_state callback to the DPU's private object. This way the debugfs/dri/0/state will also include RM's internal state. Example output (RB5 board, HDMI and writeback encoder enabled) resource mapping: pingpong=31 36 # # # # - - - - - mixer=31 36 # # # # - ctl=# # 31 36 # # dspp=# # # # dsc=# # # # - - cdm=# Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/579648/ Link: https://lore.kernel.org/r/20240222-fd-rm-state-v5-1-4a6c81e87f63@linaro.org
2024-04-02drm/msm/dpu: make error messages at dpu_core_irq_register_callback() more ↵Dmitry Baryshkov1-4/+4
sensible There is little point in using %ps to print a value known to be NULL. On the other hand it makes sense to print the callback symbol in the 'invalid IRQ' message. Correct those two error messages to make more sense. Fixes: 6893199183f8 ("drm/msm/dpu: stop using raw IRQ indices in the kernel output") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/585565/ Link: https://lore.kernel.org/r/20240330-dpu-irq-messages-v1-1-9ce782ae35f9@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
2024-03-29drm/msm/dp: assign correct DP controller ID to x1e80100 interface tableKuogee Hsieh1-3/+31
At current x1e80100 interface table, interface #3 is wrongly connected to DP controller #0 and interface #4 wrongly connected to DP controller #2. Fix this problem by connect Interface #3 to DP controller #0 and interface #4 connect to DP controller #1. Also add interface #6, #7 and #8 connections to DP controller to complete x1e80100 interface table. Changs in V3: -- add v2 changes log Changs in V2: -- add x1e80100 to subject -- add Fixes Fixes: e3b1f369db5a ("drm/msm/dpu: Add X1E80100 support") Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/585549/ Link: https://lore.kernel.org/r/1711741586-9037-1-git-send-email-quic_khsieh@quicinc.com Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
2024-03-29drm/msm/dpu: don't allow overriding data from catalogDmitry Baryshkov1-5/+5
The data from catalog is marked as const, so it is a part of the RO segment. Allowing userspace to write to it through debugfs can cause protection faults. Set debugfs file mode to read-only for debug entries corresponding to perf_cfg coming from catalog. Fixes: abda0d925f9c ("drm/msm/dpu: Mark various data tables as const") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/582844/ Link: https://lore.kernel.org/r/20240314-dpu-perf-rework-v3-1-79fa4e065574@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
2024-03-04drm/msm/dpu: capture snapshot on the first commit_done timeoutDmitry Baryshkov1-0/+10
In order to debug commit_done timeouts, capture the devcoredump state when the first timeout occurs after the encoder has been enabled. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579850/ Link: https://lore.kernel.org/r/20240226-fd-dpu-debug-timeout-v4-3-51eec83dde23@linaro.org
2024-03-04drm/msm/dpu: split dpu_encoder_wait_for_event into two functionsDmitry Baryshkov3-39/+55
Stop multiplexing several events via the dpu_encoder_wait_for_event() function. Split it into two distinct functions two allow separate handling of those events. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579848/ Link: https://lore.kernel.org/r/20240226-fd-dpu-debug-timeout-v4-2-51eec83dde23@linaro.org
2024-03-04drm/msm/dpu: make "vblank timeout" more usefulDmitry Baryshkov1-1/+1
We have several reports of vblank timeout messages. However after some debugging it was found that there might be different causes to that. To allow us to identify the DPU block that gets stuck, include the actual CTL_FLUSH value into the timeout message. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579849/ Link: https://lore.kernel.org/r/20240226-fd-dpu-debug-timeout-v4-1-51eec83dde23@linaro.org
2024-03-04drm/msm/dp: allow YUV420 mode for DP connector when CDM availablePaloma Arellano1-1/+3
All the components of YUV420 over DP are added. Therefore, let's mark the connector property as true for DP connector when the DP type is not eDP and when there is a CDM block available. Changes in v3: - Move setting the connector's ycbcr_420_allowed parameter so that it is not dependent on if the dp_display is not eDP Changes in v2: - Check for if dp_catalog has a CDM block available instead of checking if VSC SDP is allowed when setting the dp connector's ycbcr_420_allowed parameter Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579628/ Link: https://lore.kernel.org/r/20240222194025.25329-20-quic_parellan@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-03-04drm/msm/dpu: reserve CDM blocks for DP if mode is YUV420Paloma Arellano1-8/+14
Reserve CDM blocks for DP if the mode format is YUV420. Currently this reservation only works for writeback and DP if the format is YUV420. But this can be easily extented to other YUV formats for DP. Changes in v2: - Minor code simplification Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579630/ Link: https://lore.kernel.org/r/20240222194025.25329-19-quic_parellan@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-03-04drm/msm/dpu: modify timing engine programming for YUV420 over DPPaloma Arellano1-2/+6
Adjust the encoder timing engine setup programming in the case of video mode for YUV420 over DP to accommodate CDM. Changes in v3: - Move drm_display_mode's hskew division to another patch - Minor cleanup Changes in v2: - Move timing engine programming to this patch Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579634/ Link: https://lore.kernel.org/r/20240222194025.25329-18-quic_parellan@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-03-04drm/msm/dpu: modify encoder programming for CDM over DPPaloma Arellano3-0/+64
Adjust the encoder format programming in the case of video mode for DP to accommodate CDM related changes. Changes in v4: - Remove hw_cdm check in dpu_encoder_needs_periph_flush() - Remove hw_cdm check when getting the fmt_fourcc in dpu_encoder_phys_vid_enable() Changes in v2: - Move timing engine programming to a separate patch from this one - Move update_pending_flush_periph() invocation completely to this patch - Change the logic of dpu_encoder_get_drm_fmt() so that it only calls drm_mode_is_420_only() instead of doing additional unnecessary checks - Create new functions msm_dp_needs_periph_flush() and it's supporting function dpu_encoder_needs_periph_flush() to check if the mode is YUV420 and VSC SDP is enabled before doing a peripheral flush Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579641/ Link: https://lore.kernel.org/r/20240222194025.25329-17-quic_parellan@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-03-04drm/msm/dpu: add support of new peripheral flush mechanismKuogee Hsieh2-0/+27
Introduce a peripheral flushing mechanism to decouple peripheral metadata flushing from timing engine related flush. Changes in v2: - Fixed some misalignment issues Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579619/ Link: https://lore.kernel.org/r/20240222194025.25329-15-quic_parellan@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-03-04drm/msm/dpu: move widebus logic to its own APIPaloma Arellano2-13/+20
Widebus enablement is decided by the interfaces based on their specific checks and that already happens with DSI/DP specific helpers. Let's invoke these helpers from dpu_encoder_is_widebus_enabled() to make it cleaner overall. Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579632/ Link: https://lore.kernel.org/r/20240222194025.25329-10-quic_parellan@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-03-04drm/msm/dpu: move dpu_encoder_helper_phys_setup_cdm to dpu_encoderPaloma Arellano3-83/+87
Move dpu_encoder_helper_phys_setup_cdm to dpu_encoder in preparation for implementing YUV420 over DP, which requires CDM compatibility. Changes in v2: - Slightly change the wording of the commit text to make clear that YUV over DP requires CDM Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579611/ Link: https://lore.kernel.org/r/20240222194025.25329-6-quic_parellan@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-03-04drm/msm/dpu: allow dpu_encoder_helper_phys_setup_cdm to work for DPPaloma Arellano2-15/+16
Generalize dpu_encoder_helper_phys_setup_cdm to be compatible with DP. Changes in v2: - Minor formatting changes - Move the modification of the dimensions for CDM setup to a new patch Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579609/ Link: https://lore.kernel.org/r/20240222194025.25329-5-quic_parellan@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-03-04drm/msm/dpu: pass mode dimensions instead of fb size in CDM setupPaloma Arellano1-2/+2
Modify the output width and height parameters of hw_cdm to utilize the physical encoder's data instead of obtaining the information from the framebuffer. CDM is to be set up to utilize the actual output data since at CDM setup, there is no difference between the two sources. Changes in v2: - Move the modification of the dimensions for CDM setup to this new patch Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579607/ Link: https://lore.kernel.org/r/20240222194025.25329-4-quic_parellan@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-03-04drm/msm/dpu: add division of drm_display_mode's hskew parameterPaloma Arellano1-2/+4
Setting up the timing engine when the physical encoder has a split role neglects dividing the drm_display_mode's hskew parameter. Let's fix this since this must also be done in preparation for implementing YUV420 over DP. Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579605/ Link: https://lore.kernel.org/r/20240222194025.25329-3-quic_parellan@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-03-04drm/msm/dpu: allow certain formats for CDM for DPPaloma Arellano1-1/+1
CDM block supports formats other than H1V2 for DP. Since we are now adding support for CDM over DP, relax the checks to allow all other formats for DP other than H1V2. Changes in v2: - Add fixes tag - Move patch to top of series Fixes: 0afac0ba6024 ("drm/msm/dpu: add dpu_hw_cdm abstraction for CDM block") Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579606/ Link: https://lore.kernel.org/r/20240222194025.25329-2-quic_parellan@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-02-23drm/msm/dpu: Add X1E80100 supportAbel Vesa4-0/+453
Add definitions for the display hardware used on the Qualcomm X1E80100 platform. Co-developed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579075/ Link: https://lore.kernel.org/r/20240220-x1e80100-display-v4-4-971afd9de861@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-02-19drm/msm/mdp5: drop global_state_lockDmitry Baryshkov2-9/+0
Since the commit b962a12050a3 ("drm/atomic: integrate modeset lock with private objects") the DRM framework no longer requires the external lock for private objects. Drop the lock, letting the DRM to manage private object locking. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/570183/ Link: https://lore.kernel.org/r/20231203000532.1290480-6-dmitry.baryshkov@linaro.org
2024-02-19drm/msm/mdp5: migrate SMP dumping to using atomic_print_stateDmitry Baryshkov4-49/+15
The Shared Memory Pool (SMP) state is a part of the MDP5's private object state. Use existing infrastructure, atomic_print_state() callback, to dump SMP state (which also makes it included into debugfs/dri/N/state). This allows us to drop the custom debugfs file too. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/570179/ Link: https://lore.kernel.org/r/20231203000532.1290480-5-dmitry.baryshkov@linaro.org
2024-02-19drm/msm/dpu: drop global_state_lockDmitry Baryshkov2-9/+0
Since the commit b962a12050a3 ("drm/atomic: integrate modeset lock with private objects") the DRM framework no longer requires the external lock for private objects. Drop the lock, letting the DRM to manage private object locking. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/570174/ Link: https://lore.kernel.org/r/20231203000532.1290480-4-dmitry.baryshkov@linaro.org
2024-02-19drm/msm/dpu: finalise global state objectDmitry Baryshkov1-0/+8
Add calls to finalise global state object and corresponding lock. Fixes: de3916c70a24 ("drm/msm/dpu: Track resources in global state") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/570175/ Link: https://lore.kernel.org/r/20231203000532.1290480-3-dmitry.baryshkov@linaro.org
2024-02-19drm/msm/dpu: add support for SDM660 and SDM630 platformsDmitry Baryshkov5-0/+522
Bring in hardware support for the SDM660 and SDM630 platforms, which belong to the same DPU generation as MSM8998. Note, by default these platforms are still handled by the MDP5 driver unless the `msm.prefer_mdp5=false' parameter is provided. Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/577507/ Link: https://lore.kernel.org/r/20240208-fd-migrate-mdp5-v4-4-945d08ef3fa8@linaro.org
2024-02-19drm/msm: add a kernel param to select between MDP5 and DPU driversDmitry Baryshkov2-0/+6
For some of the platforms (e.g. SDM660, SDM630, MSM8996, etc.) it is possible to support this platform via the DPU driver (e.g. to provide support for DP, multirect, etc). Add a modparam to be able to switch between these two drivers. All platforms supported by both drivers are by default handled by the MDP5 driver. To let them be handled by the DPU driver pass the `msm.prefer_mdp5=false` kernel param. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Carl Vanderlip <quic_carlv@quicinc.com> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/577504/ Link: https://lore.kernel.org/r/20240208-fd-migrate-mdp5-v4-3-945d08ef3fa8@linaro.org
2024-02-19drm/msm/dpu: support binding to the mdp5 devicesDmitry Baryshkov1-21/+77
Existing MDP5 devices have slightly different bindings. The main register region is called `mdp_phys' instead of `mdp'. Also vbif register regions are a part of the parent, MDSS device. Add support for handling this binding differences. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/577505/ Link: https://lore.kernel.org/r/20240208-fd-migrate-mdp5-v4-2-945d08ef3fa8@linaro.org
2024-02-11drm/msm/dpu: drop dpu_encoder_phys_ops::atomic_check()Dmitry Baryshkov2-19/+0
Writeback was the last user of dpu_encoder_phys_ops's atomic_check() callback. As the code was moved to the dpu_writeback.c, the callback becomes unused. Drop it now. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/577528/ Link: https://lore.kernel.org/r/20240208-fd_remove_phys_ops_atomic_mode_set-v4-5-caf5dcd125c0@linaro.org
2024-02-11drm/msm/dpu: move writeback's atomic_check to dpu_writeback.cDmitry Baryshkov4-59/+68
dpu_encoder_phys_wb is the only user of encoder's atomic_check callback. Move corresponding checks to drm_writeback_connector's implementation and drop the dpu_encoder_phys_wb_atomic_check() function. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Tested-by: Paloma Arellano <quic_parellan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/577524/ Link: https://lore.kernel.org/r/20240208-fd_remove_phys_ops_atomic_mode_set-v4-4-caf5dcd125c0@linaro.org
2024-02-11drm/msm/dpu: drop dpu_encoder_phys_ops.atomic_mode_setDmitry Baryshkov5-46/+17
The atomic_mode_set() callback only sets the phys_enc's IRQ data. As the INTF and WB are statically allocated to each encoder/phys_enc, drop the atomic_mode_set callback and set the IRQs during encoder init. For the CMD panel usecase some of IRQ indexes depend on the selected resources. Move setting them to the irq_enable() callback. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Tested-by: Abhinav Kumar <quic_abhinavk@quicinc.com> # sc7280 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/577529/ Link: https://lore.kernel.org/r/20240208-fd_remove_phys_ops_atomic_mode_set-v4-3-caf5dcd125c0@linaro.org
2024-02-11drm/msm/dpu: split _dpu_encoder_resource_control_helper()Dmitry Baryshkov2-20/+37
Follow the _dpu_encoder_irq_control() change and split the _dpu_encoder_resource_control_helper() into enable and disable parts. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/577525/ Link: https://lore.kernel.org/r/20240208-fd_remove_phys_ops_atomic_mode_set-v4-2-caf5dcd125c0@linaro.org
2024-02-11drm/msm/dpu: split irq_control into irq_enable and _disableDmitry Baryshkov6-86/+158
The single helper for both enable and disable cases is too complicated, especially if we start adding more code to these helpers. Split it into irq_enable and irq_disable cases. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/577526/ Link: https://lore.kernel.org/r/20240208-fd_remove_phys_ops_atomic_mode_set-v4-1-caf5dcd125c0@linaro.org
2024-02-11drm/msm/dpu: Only enable DSC_MODE_MULTIPLEX if dsc_merge is enabledMarijn Suijten1-1/+3
When the topology calls for two interfaces on the current fixed topology of 2 DSC blocks, or uses 1 DSC block for a single interface (e.g. SC7280 with only one DSC block), there should be no merging of DSC output. This is already represented by the return value of dpu_encoder_use_dsc_merge(), but not yet used to correctly configure this flag. Fixes: 58dca9810749 ("drm/msm/disp/dpu1: Add support for DSC in encoder") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/577067/ Link: https://lore.kernel.org/r/20240204-dpu-dsc-multiplex-v1-1-080963233c52@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-02-11drm/msm/dpu: fix the programming of INTF_CFG2_DATA_HCTL_ENAbhinav Kumar5-6/+25
Currently INTF_CFG2_DATA_HCTL_EN is coupled with the enablement of widebus but this is incorrect because we should be enabling this bit independent of widebus except for cases where compression is enabled in one pixel per clock mode. Fix this by making the condition checks more explicit and enabling INTF_CFG2_DATA_HCTL_EN for all other cases when supported by DPU. Fixes: 3309a7563971 ("drm/msm/dpu: revise timing engine programming to support widebus feature") Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/576722/ Link: https://lore.kernel.org/r/20240201004737.2478-1-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-02-11drm/msm/dpu: improve DSC allocationKuogee Hsieh1-15/+139
At DSC V1.1 DCE (Display Compression Engine) contains a DSC encoder. However, at DSC V1.2 DCE consists of two DSC encoders, one has an odd index and another one has an even index. Each encoder can work independently. But only two DSC encoders from same DCE can be paired to work together to support DSC merge mode at DSC V1.2. For DSC V1.1 two consecutive DSC encoders (start with even index) have to be paired to support DSC merge mode. In addition, the DSC with even index have to be mapped to even PINGPONG index and DSC with odd index have to be mapped to odd PINGPONG index at its data path in regardless of DSC V1.1 or V1.2. This patch improves DSC allocation mechanism with consideration of those factors. Changes in V6: -- rename _dpu_rm_reserve_dsc_single to _dpu_rm_dsc_alloc -- rename _dpu_rm_reserve_dsc_pair to _dpu_rm_dsc_alloc_pair -- pass global_state to _dpu_rm_pingpong_next_index() -- remove pp_max -- fix for loop condition check at _dpu_rm_dsc_alloc() Changes in V5: -- delete dsc_id[] -- update to global_state->dsc_to_enc_id[] directly -- replace ndx with idx -- fix indentation at function declaration -- only one for loop at _dpu_rm_reserve_dsc_single() Changes in V4: -- rework commit message -- use reserved_by_other() -- add _dpu_rm_pingpong_next_index() -- revise _dpu_rm_pingpong_dsc_check() Changes in V3: -- add dpu_rm_pingpong_dsc_check() -- for pair allocation use i += 2 at for loop Changes in V2: -- split _dpu_rm_reserve_dsc() into _dpu_rm_reserve_dsc_single() and _dpu_rm_reserve_dsc_pair() Fixes: f2803ee91a41 ("drm/msm/disp/dpu1: Add DSC support in RM") Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/572144/ Link: https://lore.kernel.org/r/1702580172-30606-1-git-send-email-quic_khsieh@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-02-11drm/msm/mdp5: drop split display supportDmitry Baryshkov4-107/+0
The MSM DSI driver has dropped support for calling mdp_kms_funcs::set_split_display() callback. Drop corresponding callback from the mdp5 driver together with the rest of the infrastructure. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/561698/ Link: https://lore.kernel.org/r/20231009205727.2781802-6-dmitry.baryshkov@linaro.org
2024-01-25drm/msm/dpu: check for valid hw_pp in dpu_encoder_helper_phys_cleanupAbhinav Kumar1-2/+2
The commit 8b45a26f2ba9 ("drm/msm/dpu: reserve cdm blocks for writeback in case of YUV output") introduced a smatch warning about another conditional block in dpu_encoder_helper_phys_cleanup() which had assumed hw_pp will always be valid which may not necessarily be true. Lets fix the other conditional block by making sure hw_pp is valid before dereferencing it. Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Fixes: ae4d721ce100 ("drm/msm/dpu: add an API to reset the encoder related hw blocks") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/574878/ Link: https://lore.kernel.org/r/20240117194109.21609-1-quic_abhinavk@quicinc.com Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-01 02:10:00 +0300