Age | Commit message (Collapse) | Author | Files | Lines | |
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2013-08-31 | drm/radeon: implement clock and power gating for CIK (v3) | Alex Deucher | 1 | -0/+944 | |
Only the APUs support power gating. v2: disable cgcg for now v3: workaround hw issue in mgcg Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |