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path: root/drivers/gpu/drm/radeon/si.c
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2013-08-31drm/radeon: implement clock and power gating for CIK (v3)Alex Deucher1-1/+1
Only the APUs support power gating. v2: disable cgcg for now v3: workaround hw issue in mgcg Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon: convert SI,CIK to use sumo_rlc functionsAlex Deucher1-163/+11
and remove duplicate si_rlc functions. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-31drm/radeon/cik: restructure rlc setupAlex Deucher1-1/+1
Restructure rlc setup to handle clock and power gating. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-08drm/radeon: make missing smc ucode non-fatalAlex Deucher1-3/+7
The smc ucode is required for dpm (dynamic power management), but if it's missing just skip dpm setup and don't disable acceleration. Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=67876 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-08drm/radeon: always program the MC on startupAlex Deucher1-1/+2
For r6xx+ asics. This mirrors the behavior of pre-r6xx asics. We need to program the MC even if something else in startup() fails. Failure to do so results in an unusable GPU. Based on a fix from: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-08-08drm/radeon: fix halting UVDChristian König1-2/+4
Removing the clock/power or resetting the VCPU can cause hangs if that happens in the middle of a register write. Stall the memory and register bus before putting the VCPU into reset. Keep it in reset when unloading the module or suspending. Signed-off-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-30drm/radeon/si: disable cgcg and pg for nowAlex Deucher1-3/+3
Coarse grain clockgating causes problems with reclocking on some cards and powergating (verde only) causes problems with ring initialization. The proper fix (restructuring the init sequences) is too invasive for 3.11 so just disable them for now. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-30drm/radeon: properly handle cg on asics without UVDAlex Deucher1-6/+2
Don't try and enable clockgating if the asic doesn't have UVD. Use rdev->has_uvd rather than using local checks. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-17drm/radeon: add a module parameter to disable aspmAlex Deucher1-0/+3
Can cause hangs when enabled in certain motherboards. Set radeon.aspm=0 to disable aspm. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-14drm/radeon: add fault decode function for SI (v2)Alex Deucher1-2/+270
Helpful for debugging GPUVM errors as we can see what hw block and page generated the fault in the log. v2: simplify fault decoding Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2013-07-14drm/radeon: use radeon device for request firmwareJerome Glisse1-17/+6
Avoid creating temporary platform device that will lead to issue when several radeon gpu are in same computer. Instead directly use the radeon device for requesting firmware. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28drm/radeon/si: fix typo in function nameAlex Deucher1-2/+2
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28drm/radeon/kms: add dpm support for SI (v7)Alex Deucher1-0/+48
This adds dpm support for SI asics. This includes: - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2/gen3 switching - power containment - shader power scaling Set radeon.dpm=1 to enable. v2: enable hainan support, rebase v3: guard acpi stuff v4: fix 64 bit math v5: fix 64 bit div harder v6: fix thermal interrupt check noticed by Jerome v7: attempt fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28drm/radeon: switch SI to use radeon_ucode.hAlex Deucher1-6/+1
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28drm/radeon/dpm: save some display parameters for DPMAlex Deucher1-0/+4
Required for SI. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28drm/radeon: implement clock and power gating for SIAlex Deucher1-42/+460
Only Cape Verde supports power gating. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28drm/radeon: add clearstate init for verde power gatingAlex Deucher1-5/+63
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28drm/radeon: initialize save/restore buffer for pg on verdeAlex Deucher1-2/+241
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28drm/radeon: update rlc programming sequence on SIAlex Deucher1-0/+82
This is required for certain power management features. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28drm/radeon: add support for ASPM on SI asics (v2)Alex Deucher1-0/+203
Enables PCIE ASPM (Active State Power Management) on SI asics. v2: fix typo Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28drm/radeon: implement pcie gen2/3 support for SIAlex Deucher1-0/+162
If both the motherboard and GPU support pcie gen2 or 3, enable it. PCIE gen2 and 3 offer more bandwidth than pcie gen1. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/kms: fix up dce6 display watermark calc for dpmAlex Deucher1-25/+71
Calculate the low and high watermarks based on the low and high clocks for the current power state. The dynamic pm hw will select the appropriate watermark based on the internal dpm state. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: add support for MC/VM setup on CIK (v6)Alex Deucher1-2/+2
The vm callbacks are the same as the SI ones right now (same regs and bits). We could share the SI variants, and I may yet do that, but I figured I would add CIK specific ones for now in case we need to change anything. V2: add documentation, minor fixes. V3: integrate vram offset fixes for APUs V4: enable 2 level VM PTs V5: index SH_MEM_* regs properly V6: add ib_parse() Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-03radeon: Fix system hang issue when using KMS with older cardsAdis Hamzić1-4/+6
The current radeon driver initialization routines, when using KMS, are written so that the IRQ installation routine is called before initializing the WB buffer and the CP rings. With some ASICs, though, the IRQ routine tries to access the GFX_INDEX ring causing a call to RREG32 with the value of -1 in radeon_fence_read. This, in turn causes the system to completely hang with some cards, requiring a hard reset. A call stack that can cause such a hang looks like this (using rv515 ASIC for the example here): * rv515_init (rv515.c) * radeon_irq_kms_init (radeon_irq_kms.c) * drm_irq_install (drm_irq.c) * radeon_driver_irq_preinstall_kms (radeon_irq_kms.c) * rs600_irq_process (rs600.c) * radeon_fence_process - due to SW interrupt (radeon_fence.c) * radeon_fence_read (radeon_fence.c) * hang due to RREG32(-1) The patch moves the IRQ installation to the card startup routine, after the ring has been initialized, but before the IRQ has been set. This fixes the issue, but requires a check to see if the IRQ is already installed, as is the case in the system resume codepath. I have tested the patch on three machines using the rv515, the rv770 and the evergreen ASIC. They worked without issues. This seems to be a known issue and has been reported on several bug tracking sites by various distributions (see links below). Most of reports recommend booting the system with KMS disabled and then enabling KMS by reloading the radeon module. For some reason, this was indeed a usable workaround, however, UMS is now deprecated and disabled by default. Bug reports: https://bugzilla.redhat.com/show_bug.cgi?id=845745 https://bugs.launchpad.net/ubuntu/+source/linux/+bug/561789 https://bbs.archlinux.org/viewtopic.php?id=156964 Signed-off-by: Adis Hamzić <adis@hamzadis.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-05-29drm/radeon: fix typo in cu_per_sh on verdeAlex Deucher1-1/+1
Should be 5 rather than 2. Noticed by sroland and glisse on IRC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-05-20drm/radeon: add golden register settings for Hainan (v2)Alex Deucher1-0/+122
v2: fix typo Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2013-05-20drm/radeon: sun/hainan chips do not have UVD (v2)Alex Deucher1-28/+39
Skip UVD handling on them. v2: split has_uvd tracking into separate patch Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-20drm/radeon: fill in ucode loading support for HainanAlex Deucher1-0/+58
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2013-05-20drm/radeon: don't touch DCE or VGA regs on Hainan (v3)Alex Deucher1-40/+59
Hainan has no display hardware: - no DCE (crtc, uniphy, dac, etc.) - no VGA v2: fix bios fetch v3: fix interrupts Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2013-05-20drm/radeon: fill in GPU init for Hainan (v2)Alex Deucher1-1/+19
v2: fix gb_addr_config value Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-20drm/radeon: Fix VRAM size calculation for VRAM >= 4GBNiels Ole Salscheider1-2/+2
Add ULL prefix to avoid overflow. Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-05-02drm/radeon: consolidate UVD clock programmingChristian König1-93/+11
Instead of duplicating the code over and over again, just use a single function to handle the clock calculations. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-24drm/radeon/si: add support for golden register initAlex Deucher1-0/+793
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-24drm/radeon: fix typo in si_select_se_sh()Alex Deucher1-1/+1
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-04-22drm/radeon: put UVD PLLs in bypass modeChristian König1-8/+14
Just power down the PLL when we get a VCLK or DCLK of zero. Enabling the bypass mode early should also allow us to switch UVD clocks on the fly. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-11drm/radeon: add si tile mode array query v3Jerome Glisse1-0/+2
Allow userspace to query for the tile mode array so userspace can properly compute surface pitch and alignment requirement depending on tiling. v2: Make strict aliasing safer by casting to char when copying v3: merge fix from Christian Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-09drm/radeon: remove unused blit remnants from si.cAlex Deucher1-11/+0
We use the DMA ring rather than the GFX ring for bo moves. This code was never used and commented out. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-09drm/radeon: add UVD tiling addr config v2Christian König1-0/+3
v2: set UVD tiling config for rv730 Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2013-04-09drm/radeon: add set_uvd_clocks callback for SIChristian König1-0/+167
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-09drm/radeon: UVD bringup v8Christian König1-0/+32
Just everything needed to decode videos using UVD. v6: just all the bugfixes and support for R7xx-SI merged in one patch v7: UVD_CGC_GATE is a write only register, lockup detection fix v8: split out VRAM fallback changes, remove support for RV770, add support for HEMLOCK, add buffer sizes checks Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-09drm/radeon/dce6: add missing display reg for tiling setupAlex Deucher1-0/+1
A new tiling config register for the display blocks was added on DCE6. May fix: https://bugs.freedesktop.org/show_bug.cgi?id=62889 https://bugs.freedesktop.org/show_bug.cgi?id=57919 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-04-09drm/radeon: clean up vram/gtt location handlingAlex Deucher1-42/+2
Add a per-asic MC (memory controller) mask which holds the mak address mask the asic is capable of. Use this when calculating the vram and gtt locations rather using asic specific functions or limiting everything to 32 bits. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-03-16drm/radeon: fix S/R on VM systems (cayman/TN/SI)Alex Deucher1-0/+1
We weren't properly tearing down the VM sub-alloctor on suspend leading to bogus VM PTs on resume. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=60439 Reviewed-by: Christian König <christian.koenig@amd.com> Tested-by: Dmitry Cherkasov <Dmitrii.Cherkasov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-03-07drm/radeon: skip MC reset as it's probably not hungAlex Deucher1-0/+6
The MC is mostly likely busy (e.g., display requests), not hung so no need to reset it. Doing an MC reset is tricky and not particularly reliable. Fixes hangs in certain cases. Reported-by: Josh Boyer <jwboyer@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-02-20drm/radeon: switch get_gpu_clock() to a callback (v2)Alex Deucher1-2/+2
Cleans up the code for future asics v2: rebase, fix some missing radeon_asic updates Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-02-20drm/radeon: add a asic callback to get the xclkAlex Deucher1-0/+27
This is required to get the reference clock used by the gfx engine for things like timestamps. Fixes support for GL extensions the use timestamps on certain boards. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-02-02drm/radeon: add ucode loading support for OlandAlex Deucher1-0/+59
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-02-02drm/radeon: fill in gpu init for OlandAlex Deucher1-1/+19
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-02-01drm/radeon: use IBs for VM page table updates v2Alex Deucher1-24/+28
For very large page table updates, we can exceed the size of the ring. To avoid this, use an IB to perform the page table update. v2(ck): cleanup the IB infrastructure and the use it instead of filling the struct ourself. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com>
2013-02-01drm/radeon: use the reset mask to determine if rings are hungAlex Deucher1-20/+52
fetch the reset mask and check if the relevant ring flags are set to determine whether the ring is hung or not. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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