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AgeCommit message (Expand)AuthorFilesLines
2021-01-27stm class: Fix module init return on allocation failureWang Hui1-2/+4
2021-01-27intel_th: pci: Add Alder Lake-P supportAlexander Shishkin1-0/+5
2020-12-30coresight: tmc-etr: Check if page is valid before dma_map_page()Mao Jinlong1-0/+2
2020-08-19coresight: tmc: Fix TMC mode read in tmc_read_unprepare_etb()Sai Prakash Ranjan1-7/+6
2020-07-22intel_th: Fix a NULL dereference when hub driver is not loadedAlexander Shishkin2-6/+19
2020-07-22intel_th: pci: Add Emmitsburg PCH supportAlexander Shishkin1-0/+5
2020-07-22intel_th: pci: Add Tiger Lake PCH-H supportAlexander Shishkin1-0/+5
2020-07-22intel_th: pci: Add Jasper Lake CPU supportAlexander Shishkin1-0/+5
2020-03-25intel_th: pci: Add Elkhart Lake CPU supportAlexander Shishkin1-0/+5
2020-03-25intel_th: Fix user-visible error codesAlexander Shishkin1-3/+3
2020-01-29coresight: tmc-etf: Do not call smp_processor_id from preemptibleSuzuki K Poulose1-3/+1
2020-01-29coresight: etb10: Do not call smp_processor_id from preemptibleSuzuki K Poulose1-3/+1
2020-01-27coresight: catu: fix clang build warningArnd Bergmann2-7/+3
2020-01-27perf, pt, coresight: Fix address filters for vmas with non-zero offsetAlexander Shishkin1-3/+4
2019-12-31intel_th: pci: Add Elkhart Lake SOC supportAlexander Shishkin1-0/+5
2019-12-31intel_th: pci: Add Comet Lake PCH-V supportAlexander Shishkin1-0/+5
2019-12-17intel_th: pci: Add Tiger Lake CPU supportAlexander Shishkin1-0/+5
2019-12-17intel_th: pci: Add Ice Lake CPU supportAlexander Shishkin1-0/+5
2019-12-17intel_th: Fix a double put_device() in error pathAlexander Shishkin1-6/+2
2019-12-13coresight: etm4x: Fix input validation for sysfs.Mike Leach1-8/+13
2019-11-20coresight: dynamic-replicator: Handle multiple connectionsSuzuki K Poulose1-17/+47
2019-11-20coresight: tmc: Fix byte-address alignment for RRPLeo Yan1-2/+2
2019-11-20coresight: etm4x: Configure EL2 exception level when kernel is running in HYPTomasz Nowicki1-20/+20
2019-11-20coresight: tmc-etr: Handle driver mode specific ETR buffersSuzuki K Poulose2-20/+40
2019-11-20coresight: perf: Disable trace path upon source errorSuzuki K Poulose1-1/+3
2019-11-20coresight: perf: Fix per cpu path managementSuzuki K Poulose1-15/+40
2019-11-20coresight: Fix handling of sinksSuzuki K Poulose1-7/+15
2019-11-20coresight: Use ERR_CAST instead of ERR_PTRzhong jiang1-1/+1
2019-11-12intel_th: pci: Add Jasper Lake PCH supportAlexander Shishkin1-0/+5
2019-11-12intel_th: pci: Add Comet Lake PCH supportAlexander Shishkin1-0/+5
2019-10-11coresight: etm4x: Use explicit barriers on enable/disableAndrew Murray1-2/+12
2019-09-06intel_th: pci: Add Tiger Lake supportAlexander Shishkin1-0/+5
2019-09-06intel_th: pci: Add support for another Lewisburg PCHAlexander Shishkin1-0/+5
2019-09-06stm class: Fix a double free of stm_source_deviceDing Xiang1-1/+0
2019-07-26intel_th: msu: Fix single mode with disabled IOMMUAlexander Shishkin1-1/+1
2019-07-26intel_th: pci: Add Ice Lake NNPI supportAlexander Shishkin1-0/+5
2019-05-25intel_th: msu: Fix single mode with IOMMUAlexander Shishkin1-3/+32
2019-05-25stm class: Fix channel bitmap on 32-bit systemsAlexander Shishkin1-4/+3
2019-05-25stm class: Fix channel free in stm output free pathTingwei Zhang1-1/+1
2019-05-10intel_th: pci: Add Comet Lake supportAlexander Shishkin1-0/+5
2019-05-02intel_th: gth: Fix an off-by-one in output unassigningAlexander Shishkin1-1/+1
2019-04-20coresight: cpu-debug: Support for CA73 CPUsLeo Yan1-0/+4
2019-04-05perf/aux: Make perf_event accessible to setup_aux()Mathieu Poirier1-3/+3
2019-04-05coresight: etm4x: Add support to enable ETMv4.2Sai Prakash Ranjan1-1/+2
2019-03-23intel_th: Don't reference unassigned outputsAlexander Shishkin1-0/+4
2019-03-23stm class: Prevent division by zeroAlexander Shishkin1-3/+5
2019-03-23stm class: Fix an endless loop in channel allocationZhi Jin1-0/+3
2019-01-13intel_th: msu: Fix an off-by-one in attribute storeAlexander Shishkin1-1/+2
2018-11-13coresight: etb10: Fix handling of perf modeSuzuki K Poulose1-0/+4
2018-09-18intel_th: pci: Add Ice Lake PCH supportAlexander Shishkin1-0/+5
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