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2022-07-20irqchip: Add Loongson Extended I/O interrupt controller supportHuacai Chen1-0/+10
EIOINTC stands for "Extended I/O Interrupts" that described in Section 11.2 of "Loongson 3A5000 Processor Reference Manual". For more information please refer Documentation/loongarch/irq-chip-model.rst. Loongson-3A5000 has 4 cores per NUMA node, and each NUMA node has an EIOINTC; while Loongson-3C5000 has 16 cores per NUMA node, and each NUMA node has 4 EIOINTCs. In other words, 16 cores of one NUMA node in Loongson-3C5000 are organized in 4 groups, each group connects to an EIOINTC. We call the "group" here as an EIOINTC node, so each EIOINTC node always includes 4 cores (both in Loongson-3A5000 and Loongson- 3C5000). Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1658314292-35346-12-git-send-email-lvjianmin@loongson.cn
2022-07-20irqchip/loongson-pch-msi: Add ACPI init supportHuacai Chen1-1/+1
PCH-PIC/PCH-MSI stands for "Interrupt Controller" that described in Section 5 of "Loongson 7A1000 Bridge User Manual". For more information please refer Documentation/loongarch/irq-chip-model.rst. Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1658314292-35346-10-git-send-email-lvjianmin@loongson.cn
2022-07-20irqchip/loongson-pch-pic: Add ACPI init supportHuacai Chen1-1/+1
PCH-PIC/PCH-MSI stands for "Interrupt Controller" that described in Section 5 of "Loongson 7A1000 Bridge User Manual". For more information please refer Documentation/loongarch/irq-chip-model.rst. Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1658314292-35346-9-git-send-email-lvjianmin@loongson.cn
2022-07-20irqchip: Add Loongson PCH LPC controller supportHuacai Chen1-0/+8
PCH-LPC stands for "LPC Interrupts" that described in Section 24.3 of "Loongson 7A1000 Bridge User Manual". For more information please refer Documentation/loongarch/irq-chip-model.rst. Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1658314292-35346-8-git-send-email-lvjianmin@loongson.cn
2022-07-19Merge branch irq/renesas-irqc into irq/irqchip-nextMarc Zyngier1-0/+8
* irq/renesas-irqc: : . : New Renesas RZ/G2L IRQC driver from Lad Prabhakar, equipped with : its companion GPIO driver. : . dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/V2L SoC gpio: thunderx: Don't directly include asm-generic/msi.h pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document the properties to handle GPIO IRQ gpio: gpiolib: Allow free() callback to be overridden irqchip: Add RZ/G2L IA55 Interrupt Controller driver dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller gpio: Remove dynamic allocation from populate_parent_alloc_arg() Signed-off-by: Marc Zyngier <maz@kernel.org>
2022-07-10irqchip/sifive-plic: Make better use of the effective affinity maskSamuel Holland1-0/+1
The PLIC driver already updates the effective affinity mask in its .irq_set_affinity callback. Take advantage of that information to only touch bits (and take spinlocks) for the specific relevant hart contexts. First, make sure the effective affinity mask is set before IRQ startup. Then, since this mask already takes priv->lmask into account, checking that mask later is no longer needed (and handler->present is equivalent to the bit being set in priv->lmask). Finally, when (un)masking or changing affinity, only clear/set the enable bits in the specific old/new context(s). The cpumask operations in plic_irq_unmask() are not needed because they duplicate the code in plic_set_affinity(). Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220701202440.59059-2-samuel@sholland.org
2022-07-10irqchip: Add RZ/G2L IA55 Interrupt Controller driverLad Prabhakar1-0/+8
Add a driver for the Renesas RZ/G2L Interrupt Controller. This supports external pins being used as interrupts. It supports one line for NMI, 8 external pins and 32 GPIO pins (out of 123) to be used as IRQ lines. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220707182314.66610-4-prabhakar.mahadev-lad.rj@bp.renesas.com
2022-07-08irqchip: Add Sunplus SP7021 interrupt controller driverQin Jian1-0/+9
Add interrupt controller driver for Sunplus SP7021 SoC. This is the interrupt controller in P-chip which collects all interrupt sources in P-chip and routes them to parent interrupt controller in C-chip. Signed-off-by: Qin Jian <qinjian@cqplus1.com> Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-07genirq: GENERIC_IRQ_EFFECTIVE_AFF_MASK depends on SMPSamuel Holland1-7/+7
An IRQ's effective affinity can only be different from its configured affinity if there are multiple CPUs. Make it clear that this option is only meaningful when SMP is enabled. Most of the relevant code in irqdesc.c is already hidden behind CONFIG_SMP anyway. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220701200056.46555-4-samuel@sholland.org
2022-07-07genirq: GENERIC_IRQ_IPI depends on SMPSamuel Holland1-1/+1
The generic IPI code depends on the IRQ affinity mask being allocated and initialized. This will not be the case if SMP is disabled. Fix up the remaining driver that selected GENERIC_IRQ_IPI in a non-SMP config. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220701200056.46555-3-samuel@sholland.org
2022-07-07irqchip/mips-gic: Only register IPI domain when SMP is enabledSamuel Holland1-1/+2
The MIPS GIC irqchip driver may be selected in a uniprocessor configuration, but it unconditionally registers an IPI domain. Limit the part of the driver dealing with IPIs to only be compiled when GENERIC_IRQ_IPI is enabled, which corresponds to an SMP configuration. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220701200056.46555-2-samuel@sholland.org
2022-07-01irqchip/xilinx: Add explicit dependency on OF_ADDRESSJamie Iles1-1/+1
Commit b84dc7f0e364 ("irqchip/xilinx: Remove microblaze+zynq dependency") relaxed the dependencies on the Xilinx interrupt controller to be OF only, but some OF architectures (s390 for example) do not support OF_ADDRESS and so a build of the driver will result in undefined references to of_iomap/iounmap and friends. Fixes: b84dc7f0e364 ("irqchip/xilinx: Remove microblaze+zynq dependency") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Jamie Iles <jamie@jamieiles.com> Acked-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220630111008.3838307-1-jamie@jamieiles.com
2022-06-09irqchip/xilinx: Remove microblaze+zynq dependencyJamie Iles1-1/+1
The Xilinx IRQ controller doesn't really have any architecture dependencies - it's a generic AXI component that can be used for any FPGA core from Zynq hard processor systems to microblaze+riscv soft cores and more. Signed-off-by: Jamie Iles <jamie@jamieiles.com> Acked-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220606213952.298686-1-jamie@jamieiles.com
2022-06-03irqchip: Adjust Kconfig for LoongsonHuacai Chen1-3/+3
HTVEC will be shared by both MIPS-based and LoongArch-based Loongson processors (not only Loongson-3), so we adjust its description. HTPIC is only used by MIPS-based Loongson, so we add a MIPS dependency. Acked-by: Marc Zyngier <maz@kernel.org> Reviewed-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2022-05-26Merge tag 'asm-generic-5.19' of ↵Linus Torvalds1-11/+0
git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic Pull asm-generic updates from Arnd Bergmann: "The asm-generic tree contains three separate changes for linux-5.19: - The h8300 architecture is retired after it has been effectively unmaintained for a number of years. This is the last architecture we supported that has no MMU implementation, but there are still a few architectures (arm, m68k, riscv, sh and xtensa) that support CPUs with and without an MMU. - A series to add a generic ticket spinlock that can be shared by most architectures with a working cmpxchg or ll/sc type atomic, including the conversion of riscv, csky and openrisc. This series is also a prerequisite for the loongarch64 architecture port that will come as a separate pull request. - A cleanup of some exported uapi header files to ensure they can be included from user space without relying on other kernel headers" * tag 'asm-generic-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: h8300: remove stale bindings and symlink sparc: add asm/stat.h to UAPI compile-test coverage powerpc: add asm/stat.h to UAPI compile-test coverage mips: add asm/stat.h to UAPI compile-test coverage riscv: add linux/bpf_perf_event.h to UAPI compile-test coverage kbuild: prevent exported headers from including <stdlib.h>, <stdbool.h> agpgart.h: do not include <stdlib.h> from exported header csky: Move to generic ticket-spinlock RISC-V: Move to queued RW locks RISC-V: Move to generic spinlocks openrisc: Move to ticket-spinlock asm-generic: qrwlock: Document the spinlock fairness requirements asm-generic: qspinlock: Indicate the use of mixed-size atomics asm-generic: ticket-lock: New generic ticket-based spinlock remove the h8300 architecture
2022-05-17irqchip: Add Kconfig symbols for sunxi driversSamuel Holland1-0/+12
Not all of these drivers are needed on every ARCH_SUNXI platform. In particular, the ARCH_SUNXI symbol will be reused for the Allwinner D1, a RISC-V SoC which contains none of these irqchips. Introduce Kconfig symbols so we can select only the drivers actually used by a particular set of platforms. This also lets us move the irqchip driver dependencies to a more appropriate location. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220509034941.30704-1-samuel@sholland.org
2022-04-05irq/qcom-mpm: Fix build error without MAILBOXYueHaibing1-0/+1
If MAILBOX is n, building fails: drivers/irqchip/irq-qcom-mpm.o: In function `mpm_pd_power_off': irq-qcom-mpm.c:(.text+0x174): undefined reference to `mbox_send_message' irq-qcom-mpm.c:(.text+0x174): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `mbox_send_message' Make QCOM_MPM depends on MAILBOX to fix this. Fixes: a6199bb514d8 ("irqchip: Add Qualcomm MPM controller driver") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220317131956.30004-1-yuehaibing@huawei.com
2022-04-04Merge branch 'remove-h8300' of git://git.infradead.org/users/hch/misc into ↵Arnd Bergmann1-11/+0
asm-generic * 'remove-h8300' of git://git.infradead.org/users/hch/misc: remove the h8300 architecture This is clearly the least actively maintained architecture we have at the moment, and probably the least useful. It is now the only one that does not support MMUs at all, and most of the boards only support 4MB of RAM, out of which the defconfig kernel needs more than half just for .text/.data. Guenter Roeck did the original patch to remove the architecture in 2013 after it had already been obsolete for a while, and Yoshinori Sato brought it back in a much more modern form in 2015. Looking at the git history since the reinstantiation, it's clear that almost all commits in the tree are build fixes or cross-architecture cleanups: $ git log --no-merges --format=%an v4.5.. arch/h8300/ | sort | uniq -c | sort -rn | head -n 12 25 Masahiro Yamada 18 Christoph Hellwig 14 Mike Rapoport 9 Arnd Bergmann 8 Mark Rutland 7 Peter Zijlstra 6 Kees Cook 6 Ingo Molnar 6 Al Viro 5 Randy Dunlap 4 Yury Norov Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-03-11irqchip: Add Qualcomm MPM controller driverShawn Guo1-0/+8
Qualcomm SoCs based on the RPM architecture have a MSM Power Manager (MPM) in always-on domain. In addition to managing resources during sleep, the hardware also has an interrupt controller that monitors the interrupts when the system is asleep, wakes up the APSS when one of these interrupts occur and replays it to GIC after it becomes operational. It adds an irqchip driver for this interrupt controller, and here are some notes about it. - For given SoC, a fixed number of MPM pins are supported, e.g. 96 pins on QCM2290. Each of these MPM pins can be either a MPM_GIC pin or a MPM_GPIO pin. The mapping between MPM_GIC pin and GIC interrupt is defined by SoC, as well as the mapping between MPM_GPIO pin and GPIO number. The former mapping is retrieved from device tree, while the latter is defined in TLMM pinctrl driver. - The power domain (PD) .power_off hook is used to notify RPM that APSS is about to power collapse. This requires MPM PD be the parent PD of CPU cluster. - When SoC gets awake from sleep mode, the driver will receive an interrupt from RPM, so that it can replay interrupt for particular polarity. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220308080534.3384532-3-shawn.guo@linaro.org
2022-02-23remove the h8300 architectureChristoph Hellwig1-11/+0
Signed-off-by: Christoph Hellwig <hch@lst.de>
2021-10-25Merge branch irq/mchp-eic into irq/irqchip-nextMarc Zyngier1-0/+8
* irq/mchp-eic: : . : New irqchip driver for the Microchip EIC block : . irqchip/mchp-eic: Fix return value check in mchp_eic_init() irqchip/mchp-eic: Add support for the Microchip EIC dt-bindings: microchip,eic: Add bindings for the Microchip EIC Signed-off-by: Marc Zyngier <maz@kernel.org>
2021-10-20irqchip/irq-bcm7120-l2: Switch to IRQCHIP_PLATFORM_DRIVERFlorian Fainelli1-1/+3
Allow the user selection and building of this interrupt controller driver as a module since it is used on ARM/ARM64 based systems as a second level interrupt controller hanging off the ARM GIC and is therefore loadable during boot. To avoid using of_irq_count() which is not exported towards module, switch the driver to use the platform_device provided by the irqchip platform driver code and resolve the number of interrupts using platform_irq_count(). Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211020184859.2705451-11-f.fainelli@gmail.com
2021-10-20irqchip/irq-brcmstb-l2: Switch to IRQCHIP_PLATFORM_DRIVERFlorian Fainelli1-1/+3
Allow the user selection and building of this interrupt controller driver as a module since it is used on ARM/ARM64 based systems as a second level interrupt controller hanging off the ARM GIC and is therefore loadable during boot. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211020184859.2705451-9-f.fainelli@gmail.com
2021-10-20irqchip/irq-bcm7038-l1: Switch to IRQCHIP_PLATFORM_DRIVERFlorian Fainelli1-1/+3
Allow the user selection and building of this interrupt controller driver as a module since it is used on ARM/ARM64 based systems as a second level interrupt controller hanging off the ARM GIC and is therefore loadable during boot. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211020184859.2705451-7-f.fainelli@gmail.com
2021-10-20irqchip/mchp-eic: Add support for the Microchip EICClaudiu Beznea1-0/+8
Add support for Microchip External Interrupt Controller. The controller supports 2 external interrupt lines. For every external input there is a connection to GIC. The interrupt controllers contains only 4 registers: - EIC_GFCS (read only): which indicates that glitch filter configuration is ready (not addressed in this implementation) - EIC_SCFG0R, EIC_SCFG1R (read, write): allows per interrupt specific settings: enable, polarity/edge settings, glitch filter settings - EIC_WPMR, EIC_WPSR: enables write protection mode specific settings (which are architecture specific) for the controller and are not addressed in this implementation Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210927063657.2157676-3-claudiu.beznea@microchip.com
2021-10-20irqchip/meson-gpio: Make it possible to build as a moduleNeil Armstrong1-2/+3
In order to reduce the kernel Image size on multi-platform distributions, make it possible to build the Amlogic GPIO IRQ controller as a module by switching it to a platform driver. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Saravana Kannan <saravanak@google.com> Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210902134914.176986-2-narmstrong@baylibre.com
2021-09-22irqchip/goldfish-pic: Select GENERIC_IRQ_CHIP to fix buildRandy Dunlap1-0/+1
irq-goldfish-pic uses GENERIC_IRQ_CHIP interfaces so select that symbol to fix build errors. Fixes these build errors: mips-linux-ld: drivers/irqchip/irq-goldfish-pic.o: in function `goldfish_pic_of_init': irq-goldfish-pic.c:(.init.text+0xc0): undefined reference to `irq_alloc_generic_chip' mips-linux-ld: irq-goldfish-pic.c:(.init.text+0xf4): undefined reference to `irq_gc_unmask_enable_reg' mips-linux-ld: irq-goldfish-pic.c:(.init.text+0xf8): undefined reference to `irq_gc_unmask_enable_reg' mips-linux-ld: irq-goldfish-pic.c:(.init.text+0x100): undefined reference to `irq_gc_mask_disable_reg' mips-linux-ld: irq-goldfish-pic.c:(.init.text+0x104): undefined reference to `irq_gc_mask_disable_reg' mips-linux-ld: irq-goldfish-pic.c:(.init.text+0x11c): undefined reference to `irq_setup_generic_chip' mips-linux-ld: irq-goldfish-pic.c:(.init.text+0x168): undefined reference to `irq_remove_generic_chip' Fixes: 4235ff50cf98 ("irqchip/irq-goldfish-pic: Add Goldfish PIC driver") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: kernel test robot <lkp@intel.com> Cc: Miodrag Dinic <miodrag.dinic@mips.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Marc Zyngier <maz@kernel.org> Cc: Goran Ferenc <goran.ferenc@mips.com> Cc: Aleksandar Markovic <aleksandar.markovic@mips.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210905162519.21507-1-rdunlap@infradead.org
2021-06-06irqchip/qcom-pdc: Switch to IRQCHIP_PLATFORM_DRIVER and allow as a moduleSaravana Kannan1-1/+1
This patch revives changes from Saravana Kannan to switch the qcom-pdc driver to use IRQCHIP_PLATFORM_DRIVER helper macros, and allows qcom-pdc driver to be loaded as a permanent module. Earlier attempts at this ran into trouble with loading dependencies, but with Saravana's fw_devlink=on set by default now we should avoid those. [jstultz: Folded in with my changes to allow the driver to be loadable as a permenent module] Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Joerg Roedel <joro@8bytes.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <maz@kernel.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Maulik Shah <mkshah@codeaurora.org> Cc: Lina Iyer <ilina@codeaurora.org> Cc: Saravana Kannan <saravanak@google.com> Cc: Todd Kjos <tkjos@google.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: linux-arm-msm@vger.kernel.org Cc: iommu@lists.linux-foundation.org Cc: linux-gpio@vger.kernel.org Signed-off-by: Saravana Kannan <saravanak@google.com> Signed-off-by: John Stultz <john.stultz@linaro.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210518211922.3474368-1-john.stultz@linaro.org
2021-05-10irqchip/apple-aic: APPLE_AIC should depend on ARCH_APPLEGeert Uytterhoeven1-1/+1
The Apple Interrupt Controller is only present on Apple Silicon SoCs. Hence add a dependency on ARCH_APPLE, to prevent asking the user about this driver when configuring a kernel without Apple Silicon SoC support. Drop the default, as ARCH_APPLE already selects APPLE_AIC. Fixes: 76cde26394114f6a ("irqchip/apple-aic: Add support for the Apple Interrupt Controller") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/f37e8daea37d50651d2164b0b3dad90780188548.1618316398.git.geert+renesas@glider.be
2021-04-26Merge tag 'arm-apple-m1-5.13' of ↵Linus Torvalds1-0/+8
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM Apple M1 platform support from Arnd Bergmann: "The Apple M1 is the processor used it all current generation Apple Macintosh computers. Support for this platform so far is rudimentary, but it boots and can use framebuffer and serial console over a special USB cable. Support for several essential on-chip devices (USB, PCIe, IOMMU, NVMe) is work in progress but was not ready in time. A very detailed description of what works is in the commit message of commit 1bb2fd3880d4 ("Merge tag 'm1-soc-bringup-v5' [..]") and on the AsahiLinux wiki" Link: https://lore.kernel.org/linux-arm-kernel/bdb18e9f-fcd7-1e31-2224-19c0e5090706@marcan.st/ * tag 'arm-apple-m1-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: asm-generic/io.h: Unbork ioremap_np() declaration arm64: apple: Add initial Apple Mac mini (M1, 2020) devicetree dt-bindings: display: Add apple,simple-framebuffer arm64: Kconfig: Introduce CONFIG_ARCH_APPLE irqchip/apple-aic: Add support for the Apple Interrupt Controller dt-bindings: interrupt-controller: Add DT bindings for apple-aic arm64: Move ICH_ sysreg bits from arm-gic-v3.h to sysreg.h of/address: Add infrastructure to declare MMIO as non-posted asm-generic/io.h: implement pci_remap_cfgspace using ioremap_np arm64: Implement ioremap_np() to map MMIO as nGnRnE docs: driver-api: device-io: Document ioremap() variants & access funcs docs: driver-api: device-io: Document I/O access functions asm-generic/io.h: Add a non-posted variant of ioremap() arm64: arch_timer: Implement support for interrupt-names dt-bindings: timer: arm,arch_timer: Add interrupt-names support arm64: cputype: Add CPU implementor & types for the Apple M1 cores dt-bindings: arm: cpus: Add apple,firestorm & icestorm compatibles dt-bindings: arm: apple: Add bindings for Apple ARM platforms dt-bindings: vendor-prefixes: Add apple prefix
2021-04-24irqchip/xilinx: Expose Kconfig option for Zynq/ZynqMPRobert Hancock1-1/+6
Previously the XILINX_INTC config option was hidden and only auto-selected on the MicroBlaze platform. However, this IP can also be used on the Zynq and ZynqMP platforms as a secondary cascaded controller. Allow this option to be user-enabled on those platforms. Signed-off-by: Robert Hancock <robert.hancock@calian.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210423185853.2556087-1-robert.hancock@calian.com
2021-04-22irqchip: Add support for IDT 79rc3243x interrupt controllerThomas Bogendoerfer1-0/+5
IDT 79rc3243x SoCs have rather simple interrupt controllers connected to the MIPS CPU interrupt lines. Each of them has room for up to 32 interrupts. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210422145330.73452-1-tsbogend@alpha.franken.de
2021-04-08irqchip/apple-aic: Add support for the Apple Interrupt ControllerHector Martin1-0/+8
This is the root interrupt controller used on Apple ARM SoCs such as the M1. This irqchip driver performs multiple functions: * Handles both IRQs and FIQs * Drives the AIC peripheral itself (which handles IRQs) * Dispatches FIQs to downstream hard-wired clients (currently the ARM timer). * Implements a virtual IPI multiplexer to funnel multiple Linux IPIs into a single hardware IPI Reviewed-by: Marc Zyngier <maz@kernel.org> Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-04-08irqchip/wpcm450: Drop COMPILE_TESTMarc Zyngier1-1/+1
This driver is (for now) ARM specific, and currently doesn't build with a variety of architectures (ia64, RISC-V, x86_64 at the very least). Drop COMPILE_TEST from Kconfig until it gets sorted out. Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Marc Zyngier <maz@kernel.org>
2021-04-07irqchip: Add driver for WPCM450 interrupt controllerJonathan Neuschäfer1-0/+6
The WPCM450 AIC ("Advanced Interrupt Controller") is the interrupt controller found in the Nuvoton WPCM450 SoC and other Winbond/Nuvoton SoCs. The list of registers if based on the AMI vendor kernel and the Nuvoton W90N745 datasheet. Although the hardware supports other interrupt modes, the driver only supports high-level interrupts at the moment, because other modes could not be tested so far. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210406120921.2484986-7-j.neuschaefer@gmx.net
2021-03-08irqchip: Do not blindly select CONFIG_GENERIC_IRQ_MULTI_HANDLERMarc Zyngier1-9/+0
Implementing CONFIG_GENERIC_IRQ_MULTI_HANDLER is a decision that is made at the architecture level, and shouldn't involve the irqchip at all (we even provide a fallback helper when the option isn't selected). Drop all instances of such selection from non-arch code. Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210217142800.2547737-1-maz@kernel.org Signed-off-by: Mark Rutland <mark.rutland@arm.com> Tested-by: Hector Martin <marcan@marcan.st> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Will Deacon <will@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org>
2021-02-15Merge tag 'irqchip-5.12' of ↵Thomas Gleixner1-7/+3
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core Pull irqchip updates from Marc Zyngier - New driver for the MIPS-based Realtek RTL838x/RTL839x SoC - Conversion of the sun6i-r support code to a hierarchical setup - Fix wake-up interrupts for the ls-extirq driver - Fix MSI allocation for the loongson-pch-msi driver - Add compatible strings for new Qualcomm SoCs - Tidy up a few Kconfig entries (IMX, CSKY) - Spelling phyksiz - Remove the sirfsoc and tango drivers Link: https://lore.kernel.org/r/20210214124015.3333457-1-maz@kernel.org
2021-02-14irqchip/imx: IMX_INTMUX should not default to y, unconditionallyGeert Uytterhoeven1-1/+2
Merely enabling CONFIG_COMPILE_TEST should not enable additional code. To fix this, restrict the automatic enabling of IMX_INTMUX to ARCH_MXC, and ask the user in case of compile-testing. Fixes: 66968d7dfc3f5451 ("irqchip: Add COMPILE_TEST support for IMX_INTMUX") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210208145605.422943-1-geert+renesas@glider.be
2021-02-04irqchip/csky-mpintc: Prevent selection on unsupported platformsGuo Ren1-1/+1
The irq-csky-mpintc driver is only supported on CPU_CK860 and it will generate a compilation error when selected with CPU_CK610. As it is already selected directly in the architecture Kconfig, drop the option to select it manually. Signed-off-by: Guo Ren <guoren@linux.alibaba.com> [maz: rewrote commit message] Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210204074609.3553018-1-guoren@kernel.org
2021-01-21irqchip: Remove sigma tango driverArnd Bergmann1-5/+0
The tango platform is getting removed, so the driver is no longer needed. Cc: Marc Gonzalez <marc.w.gonzalez@free.fr> Cc: Mans Rullgard <mans@mansr.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210120133008.2421897-2-arnd@kernel.org
2021-01-10irqchip/pruss: Simplify the TI_PRUSS_INTC KconfigSuman Anna1-2/+3
The TI PRUSS INTC irqchip driver handles the local interrupt controller which is a child device of it's parent PRUSS/ICSSG device. The driver was upstreamed in parallel with the PRUSS platform driver, and was configurable independently previously. The PRUSS interrupt controller is an integral part of the overall PRUSS software architecture, and is not useful at all by itself. Simplify the TI_PRUSS_INTC Kconfig dependencies by making it silent and selected automatically when the TI_PRUSS platform driver is enabled. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: David Lechner <david@lechnology.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210108162901.6003-1-s-anna@ti.com
2020-12-11drivers/irqchip: Remove EZChip NPS interrupt controllerVineet Gupta1-7/+0
NPS platform has been removed from ARC port and there are no in-tree users of it now. So RIP ! Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <maz@kernel.org> Cc: linux-kernel@vger.kernel.org Link: https://lore.kernel.org/r/20201105212210.1891598-3-vgupta@synopsys.com
2020-11-08Merge tag 'irq-urgent-2020-11-08' of ↵Linus Torvalds1-2/+1
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq fixes from Thomas Gleixner: "A set of fixes for interrupt chip drivers: - Fix the fallout of the IPI as interrupt conversion in Kconfig and the BCM2836 interrupt chip driver - Fixes for interrupt affinity setting and the handling of hierarchical irq domains in the SiFive PLIC driver - Make the unmapped event handling in the TI SCI driver work correctly - A few minor fixes and cleanups in various chip drivers and Kconfig" * tag 'irq-urgent-2020-11-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: dt-bindings: irqchip: ti, sci-inta: Fix diagram indentation for unmapped events irqchip/ti-sci-inta: Add support for unmapped event handling dt-bindings: irqchip: ti, sci-inta: Update for unmapped event handling irqchip/renesas-intc-irqpin: Merge irlm_bit and needs_irlm irqchip/sifive-plic: Fix chip_data access within a hierarchy irqchip/sifive-plic: Fix broken irq_set_affinity() callback irqchip/stm32-exti: Add all LP timer exti direct events support irqchip/bcm2836: Fix missing __init annotation irqchip/mips: Drop selection of IRQ_DOMAIN_HIERARCHY irqchip/mst: Make mst_intc_of_init static irqchip/mst: MST_IRQ should depend on ARCH_MEDIATEK or ARCH_MSTARV7 genirq: Let GENERIC_IRQ_IPI select IRQ_DOMAIN_HIERARCHY
2020-10-16irqchip/mips: Drop selection of IRQ_DOMAIN_HIERARCHYMarc Zyngier1-2/+0
Now that GENERIC_IRQ_IPI selects IRQ_DOMAIN_HIERARCHY, there is no need to have this conditional select for IRQ_MIPS_CPU. Similarily, MIPS_GIC only needs selecting GENERIC_IRQ_IPI. Suggested-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-10-16irqchip/mst: MST_IRQ should depend on ARCH_MEDIATEK or ARCH_MSTARV7Geert Uytterhoeven1-0/+1
The MStar interrupt controller is only found on MStar, SigmaStar, and Mediatek SoCs. Hence add dependencies on ARCH_MEDIATEK and ARCH_MSTARV7, to prevent asking the user about the MStar interrupt controller driver when configuring a kernel without support for MStar, SigmaStar, and Mediatek SoCs. Fixes: ad4c938c92af9130 ("irqchip/irq-mst: Add MStar interrupt controller support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Daniel Palmer <daniel@thingy.jp> Link: https://lore.kernel.org/r/20201014131703.18021-1-geert+renesas@glider.be
2020-10-15Merge tag 'mfd-next-5.10' of ↵Linus Torvalds1-0/+8
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd Pull MFD updates from Lee Jones: "New Drivers: - Add support for initialising shared (between children) Regmaps - Add support for Kontron SL28CPLD - Add support for ENE KB3930 Embedded Controller - Add support for Intel FPGA PAC MAX 10 BMC New Device Support: - Add support for Power to Ricoh RN5T618 - Add support for UART to Intel Lakefield - Add support for LP87524_Q1 to Texas Instruments LP87565 New Functionality: - Device Tree; ene-kb3930, sl28cpld, syscon, lp87565, lp87524-q1 - Use new helper dev_err_probe(); madera-core, stmfx, wcd934x - Use new GPIOD API; dm355evm_msp - Add wake-up capability; sprd-sc27xx-spi - Add ACPI support; kempld-core Fix-ups: - Trivial (spelling/whitespace); Kconfig, ab8500 - Fix for unused variables; khadas-mcu, kempld-core - Remove unused header file(s); mt6360-core - Use correct IRQ flags in docs; act8945a, gateworks-gsc, rohm,bd70528-pmic - Add COMPILE_TEST support; asic3, tmio_core - Add dependency on I2C; SL28CPLD Bug Fixes: - Fix memory leak(s); sm501 - Do not free regmap_config's 'name' until exit; syscon" * tag 'mfd-next-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (34 commits) mfd: kempld-core: Fix unused variable 'kempld_acpi_table' when !ACPI mfd: sl28cpld: Depend on I2C mfd: asic3: Build if COMPILE_TEST=y dt-bindings: mfd: Correct interrupt flags in examples mfd: Add ACPI support to Kontron PLD driver mfd: intel-m10-bmc: Add Intel MAX 10 BMC chip support for Intel FPGA PAC mfd: lp87565: Add LP87524-Q1 variant dt-bindings: mfd: Add LP87524-Q1 dt-bindings: mfd: lp87565: Convert to yaml mfd: mt6360: Remove unused include <linux/version.h> mfd: sm501: Fix leaks in probe() mfd: syscon: Don't free allocated name for regmap_config dt-bindings: mfd: syscon: Document Exynos3 and Exynos5433 compatibles dt-bindings: mfd: syscon: Merge Samsung Exynos Sysreg bindings dt-bindings: mfd: ab8500: Remove weird Unicode characters mfd: sprd: Add wakeup capability for PMIC IRQ mfd: intel-lpss: Add device IDs for UART ports for Lakefield mfd: dm355evm_msp: Convert LEDs to GPIO descriptor table mfd: wcd934x: Simplify with dev_err_probe() mfd: stmfx: Simplify with dev_err_probe() ...
2020-10-10Merge branch 'irq/mstar' into irq/irqchip-nextMarc Zyngier1-0/+8
Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-10-10irqchip/irq-mst: Add MStar interrupt controller supportMark-PK Tsai1-0/+8
Add MStar interrupt controller support using hierarchy irq domain. Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Daniel Palmer <daniel@thingy.jp> Link: https://lore.kernel.org/r/20200902063344.1852-2-mark-pk.tsai@mediatek.com
2020-09-28Merge branch 'irq/ipi-as-irq', remote-tracking branches 'origin/irq/dw' and ↵Marc Zyngier1-1/+1
'origin/irq/owl' into irq/irqchip-next Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-09-25irqchip/dw-apb-ictl: Add primary interrupt controller supportZhen Lei1-1/+1
Add support to use dw-apb-ictl as primary interrupt controller. Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> [maz: minor fixups] Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Haoyu Lv <lvhaoyu@huawei.com> Link: https://lore.kernel.org/r/20200924071754.4509-4-thunder.leizhen@huawei.com
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-05 12:08:38 +0300