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linux-rolling-lts
linux-rolling-stable
master
Linux kernel stable tree (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
media
/
i2c
/
ccs-pll.c
Age
Commit message (
Expand
)
Author
Files
Lines
2023-08-10
media: ccs-pll: Initialise best_div to avoid a compiler warning
Sakari Ailus
1
-1
/
+1
2021-02-01
Merge tag 'v5.11-rc6' into patchwork
Mauro Carvalho Chehab
1
-7
/
+1
2021-01-12
media: Revert "media: ccs-pll: Fix MODULE_LICENSE"
Sakari Ailus
1
-1
/
+1
2021-01-12
media: ccs-pll: Switch from standard integer types to kernel ones
Sakari Ailus
1
-57
/
+57
2021-01-07
media: ccs-pll: Fix link frequency for C-PHY
Sakari Ailus
1
-7
/
+1
2020-12-07
media: ccs-pll: Print pixel rates
Sakari Ailus
1
-0
/
+5
2020-12-07
media: ccs-pll: Add support for DDR OP system and pixel clocks
Sakari Ailus
1
-20
/
+44
2020-12-07
media: ccs: Dual PLL support
Sakari Ailus
1
-2
/
+7
2020-12-07
media: ccs-pll: Add trivial dual PLL support
Sakari Ailus
1
-22
/
+195
2020-12-07
media: ccs-pll: Separate VT divisor limit calculation from the rest
Sakari Ailus
1
-27
/
+37
2020-12-07
media: ccs-pll: Fix VT post-PLL divisor calculation
Sakari Ailus
1
-5
/
+7
2020-12-07
media: ccs-pll: Make VT divisors 16-bit
Sakari Ailus
1
-26
/
+25
2020-12-07
media: ccs-pll: Rework bounds checks
Sakari Ailus
1
-57
/
+91
2020-12-07
media: ccs-pll: Print relevant information on PLL tree
Sakari Ailus
1
-19
/
+66
2020-12-07
media: ccs-pll: Better separate OP and VT sub-tree calculation
Sakari Ailus
1
-23
/
+31
2020-12-07
media: ccs-pll: Check for derating and overrating, support non-derating sensors
Sakari Ailus
1
-29
/
+55
2020-12-07
media: ccs-pll: Split off VT subtree calculation
Sakari Ailus
1
-124
/
+131
2020-12-07
media: ccs-pll: Add C-PHY support
Sakari Ailus
1
-9
/
+26
2020-12-07
media: ccs-pll: Add sanity checks
Sakari Ailus
1
-0
/
+9
2020-12-07
media: ccs-pll: Add support flexible OP PLL pixel clock divider
Sakari Ailus
1
-7
/
+19
2020-12-07
media: ccs-pll: Support two cycles per pixel on OP domain
Sakari Ailus
1
-6
/
+13
2020-12-07
media: ccs-pll: Add support for extended input PLL clock divider
Sakari Ailus
1
-1
/
+3
2020-12-07
media: ccs-pll: Add support for decoupled OP domain calculation
Sakari Ailus
1
-15
/
+7
2020-12-07
media: ccs-pll: Add support for lane speed model
Sakari Ailus
1
-11
/
+25
2020-12-07
media: ccs-pll: Use explicit 32-bit unsigned type
Sakari Ailus
1
-2
/
+2
2020-12-07
media: ccs-pll: Fix check for PLL multiplier upper bound
Sakari Ailus
1
-2
/
+1
2020-12-07
media: ccs-pll: Fix comment on check against maximum PLL multiplier
Sakari Ailus
1
-1
/
+1
2020-12-07
media: ccs-pll: Avoid overflow in pre-PLL divisor lower bound search
Sakari Ailus
1
-2
/
+9
2020-12-07
media: ccs-pll: Fix condition for pre-PLL divider lower bound
Sakari Ailus
1
-1
/
+1
2020-12-07
media: ccs-pll: Begin calculation from OP system clock frequency
Sakari Ailus
1
-8
/
+4
2020-12-07
media: ccs-pll: Differentiate between CSI-2 D-PHY and C-PHY
Sakari Ailus
1
-1
/
+1
2020-12-07
media: ccs-pll: Remove parallel bus support
Sakari Ailus
1
-5
/
+0
2020-12-07
media: ccs-pll: End search if there are no better values available
Sakari Ailus
1
-2
/
+8
2020-12-07
media: ccs-pll: Use correct VT divisor for calculating VT SYS divisor
Sakari Ailus
1
-2
/
+2
2020-12-07
media: ccs-pll: Split limits and PLL configuration into front and back parts
Sakari Ailus
1
-136
/
+146
2020-12-07
media: ccs-pll: Don't use div_u64 to divide a 32-bit number
Sakari Ailus
1
-1
/
+1
2020-12-03
media: ccs: Change my e-mail address
Sakari Ailus
1
-2
/
+2
2020-12-03
media: ccs-pll: Fix MODULE_LICENSE
Sakari Ailus
1
-1
/
+1
2020-12-03
media: smiapp-pll: Rename as ccs-pll
Sakari Ailus
1
-0
/
+480