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path: root/drivers/mfd/intel-lpss-pci.c
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2024-05-10mfd: intel-lpss: Switch over to MSI interruptsAndy Shevchenko1-1/+1
Some devices support MSI interrupts. Let's at least try to use them in platforms that provide MSI capability. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20240312165905.1764507-1-andriy.shevchenko@linux.intel.com Signed-off-by: Lee Jones <lee@kernel.org>
2024-02-23mfd: intel-lpss: Introduce QUIRK_CLOCK_DIVIDER_UNITY for XPS 9530Aleksandrs Vinarskis1-0/+5
Some devices (eg. Dell XPS 9530, 2023) due to a firmware bug have a misconfigured clock divider, which should've been 1:1. This introduces quirk which conditionally re-configures the clock divider to 1:1. Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231221185142.9224-3-alex.vinarskis@gmail.com Signed-off-by: Lee Jones <lee@kernel.org>
2024-02-23mfd: intel-lpss: Switch to generalized quirk tableAleksandrs Vinarskis1-8/+15
Introduce generic quirk table, and port existing walkaround for select Microsoft devices to it. This is a preparation for QUIRK_CLOCK_DIVIDER_UNITY. Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231221185142.9224-2-alex.vinarskis@gmail.com Signed-off-by: Lee Jones <lee@kernel.org>
2023-12-07mfd: intel-lpss: Don't fail probe on success of pci_alloc_irq_vectors()Andy Shevchenko1-1/+1
The pci_alloc_irq_vectors() returns a positive number on success. Hence we have to filter the negative numbers for error condition. Update the check accordingly. Fixes: e6951fb78787 ("mfd: intel-lpss: Use PCI APIs instead of dereferencing") Reported-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Link: https://lore.kernel.org/r/20231130143206.1475831-1-andriy.shevchenko@linux.intel.com Signed-off-by: Lee Jones <lee@kernel.org>
2023-12-07mfd: intel-lpss: Provide Intel LPSS PM ops structureAndy Shevchenko1-3/+2
With the help of EXPORT_NS_GPL_DEV_PM_OPS() and other *_PM_OPS() macros we may convert PM ops functions to become static. This also takes into account the PM configuration options such as CONFIG_PM and CONFIG_PM_SLEEP. This all removes a lot of ugly macros and ifdeffery in the driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231124200258.3682979-6-andriy.shevchenko@linux.intel.com Signed-off-by: Lee Jones <lee@kernel.org>
2023-12-07mfd: intel-lpss: Move exported symbols to INTEL_LPSS namespaceAndy Shevchenko1-0/+1
Avoid unnecessary pollution of the global symbol namespace by moving library functions in to a specific namespace and import that into the drivers that make use of the functions. For more info: https://lwn.net/Articles/760045/ Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231124200258.3682979-5-andriy.shevchenko@linux.intel.com Signed-off-by: Lee Jones <lee@kernel.org>
2023-12-07mfd: intel-lpss: Adjust header inclusionsAndy Shevchenko1-2/+6
Adjust header inclusions to avoid "proxy" headers and explicitly include what we are using. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231124200258.3682979-4-andriy.shevchenko@linux.intel.com Signed-off-by: Lee Jones <lee@kernel.org>
2023-12-07mfd: intel-lpss: Use device_get_match_data()Andy Shevchenko1-2/+2
Use preferred device_get_match_data() instead of acpi_match_device() to get the driver match data. With this, adjust the includes to explicitly include the correct headers. Introduce a temporary variable in PCI glue driver to be consistent with ACPI one on the same matter. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231124200258.3682979-3-andriy.shevchenko@linux.intel.com Signed-off-by: Lee Jones <lee@kernel.org>
2023-12-07mfd: intel-lpss: Revert "Add missing check for platform_get_resource"Andy Shevchenko1-0/+1
This reverts commit d918e0d5824495a75d00b879118b098fcab36fdb. The commit in question does not fix anything and only introduces a duplication in the code. The main intel_lpss_probe() performs all necessary checks. While at it and in order of avoiding similar patches to come, add a comment. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231124200258.3682979-2-andriy.shevchenko@linux.intel.com Signed-off-by: Lee Jones <lee@kernel.org>
2023-12-07mfd: intel-lpss: Use PCI APIs instead of dereferencingAndy Shevchenko1-2/+6
We have a few PCI APIs that may be used instead of direct dereferencing, Using them will also provide better error codes. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231106184052.1166579-2-andriy.shevchenko@linux.intel.com Signed-off-by: Lee Jones <lee@kernel.org>
2023-11-01mfd: intel-lpss: Add Intel Lunar Lake-M PCI IDsJarkko Nikula1-0/+13
Add Intel Lunar Lake-M SoC PCI IDs. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Link: https://lore.kernel.org/r/20231002083344.75611-1-jarkko.nikula@linux.intel.com Signed-off-by: Lee Jones <lee@kernel.org>
2023-04-26mfd: intel-lpss: Add Intel Meteor Lake PCH-S LPSS PCI IDsJarkko Nikula1-0/+15
Add Intel Meteor Lake PCH-S also called as Meteor Point-S LPSS PCI IDs. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/20230330132618.4108665-1-jarkko.nikula@linux.intel.com
2022-09-28mfd: intel-lpss: Provide an SSP type to the SPI driverAndy Shevchenko1-46/+95
The SPI driver wants to know the exact type of the controller. Provide this information to it. This is a complementary part to the previously updated intel-lpss-acpi.c. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/20220702211903.9093-1-andriy.shevchenko@linux.intel.com
2022-07-19mfd: intel-lpss: Add Intel Meteor Lake-P PCI IDsAndy Shevchenko1-0/+13
Add Intel Meteor Lake-P LPSS PCI IDs. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20220628223047.34301-1-andriy.shevchenko@linux.intel.com
2022-05-23mfd: intel-lpss: Add support for ADL-P i2c6 and i2c7Gaggery Tsai1-0/+2
Added 8086:51d8 and 8086:51d9 to the intel_lpss_pci driver. They are Intel Alder Lake-P i2c controllers. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20220520193537.26090-1-gaggery.tsai@intel.com
2022-03-08mfd: intel-lpss: Add Intel Raptor Lake PCH-S PCI IDsJarkko Nikula1-0/+15
Add Intel Raptor Lake PCH-S LPSS PCI IDs. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20220211145055.992179-1-jarkko.nikula@linux.intel.com
2021-12-29mfd: intel-lpss: Fix I2C4 not being available on the Microsoft Surface Go & Go 2Hans de Goede1-0/+12
Many DSDTs for Kaby Lake and Kaby Lake Refresh models contain a _SB.PCI0.GEXP ACPI Device node describing an I2C attached PCA953x GPIO expander. This seems to be something which is copy and pasted from the DSDT from some reference design since this ACPI Device is present even on models where no such GPIO expander is used at all, such as on the Microsoft Surface Go & Go 2. This ACPI Device is a problem because it contains a SystemMemory OperationRegion which covers the MMIO for the I2C4 I2C controller. This causes the MFD cell for the I2C4 controller to not be instantiated due to a resource conflict, requiring the use of acpi_enforce_resources=lax to work around this. I have done an extensive analysis of all the ACPI tables on the Microsoft Surface Go and the _SB.PCI0.GEXP ACPI Device's methods are not used by any code in the ACPI tables, neither are any of them directly called by any Linux kernel code. This is unsurprising since running i2cdetect on the I2C4 bus shows that there is no GPIO expander chip present on these devices at all. This commit adds a PCI subsystem vendor:device table listing PCI devices where it is known to be safe to ignore resource conflicts with ACPI declared SystemMemory regions. This makes the I2C4 bus work out of the box on the Microsoft Surface Go & Go 2, which is necessary for the cameras on these devices to work. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20211203115108.89661-1-hdegoede@redhat.com
2021-11-29mfd: intel-lpss-pci: Fix clock speed for 38a8 UARTOrlando Chamberlain1-1/+1
This device is found in the MacBookPro16,2, and as the MacBookPro16,1 is from the same generation of MacBooks and has a UART with bxt_uart_info, it was incorrectly assumed that the MacBookPro16,2's UART would have the same info. This led to the wrong clock speed being used, and the Bluetooth controller exposed by the UART receiving and sending random data, which was incorrectly assumed to be an issue with the Bluetooth stuff, not an error with the UART side of things. Changing the info to spt_uart_info changes the clock speed and makes it send and receive data correctly. Fixes: ddb1ada416fd ("mfd: intel-lpss: Add support for MacBookPro16,2 ICL-N UART") Signed-off-by: Orlando Chamberlain <redecorating@protonmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20211124091846.11114-1-redecorating@protonmail.com
2021-11-29mfd: intel-lpss: Add Intel Lakefield PCH PCI IDsEd Schaller1-0/+7
Add new IDs of the Intel Lakefield chip to the list of supported devices. Signed-off-by: Ed Schaller <schallee@darkmist.net> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20211123180114.GA4747@darkmist.net
2021-11-05mfd: intel-lpss: Add support for MacBookPro16,2 ICL-N UARTOrlando Chamberlain1-0/+2
Added 8086:38a8 to the intel_lpss_pci driver. It is an Intel Ice Lake PCH-N UART controler present on the MacBookPro16,2. Signed-off-by: Orlando Chamberlain <redecorating@protonmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20211002111449.12674-1-redecorating@protonmail.com
2021-06-02mfd: intel-lpss: Add Intel Alder Lake-M PCI IDsAndy Shevchenko1-0/+13
Add Intel Alder Lake-M LPSS PCI IDs. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2021-04-14mfd: intel-lpss: Switch to use the software nodesHeikki Krogerus1-8/+28
Software node was always created for the device if it was supplied with additional device properties, so those nodes might as well be constant. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2021-04-14mfd: intel-lpss: Constify device property structuresAndy Shevchenko1-5/+5
There is no point to have non-constant device properties in this driver. Thus, constify them for good. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2021-02-08mfd: intel-lpss: Add Intel Alder Lake PCH-S PCI IDsJarkko Nikula1-0/+15
Add Intel Alder Lake LPSS PCI IDs. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2021-02-08mfd: intel-lpss: Add Intel Alder Lake PCH-P PCI IDsAndy Shevchenko1-0/+13
Add Intel Alder Lake LPSS PCI IDs. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2020-09-30mfd: intel-lpss: Add device IDs for UART ports for LakefieldAndy Shevchenko1-0/+4
Add PCI IDs for Lakefield to the list of supported UARTs. Cc: Jarkko Nikula <jarkko.nikula@linux.intel.com> Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: "Ravi V. Shankar" <ravi.v.shankar@intel.com> Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2020-06-30mfd: intel-lpss: Add Intel Tiger Lake PCH-H PCI IDsAndy Shevchenko1-0/+16
Intel Tiger Lake PCH-H has the same LPSS than Intel Broxton. Add the new IDs to the list of supported devices. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2020-06-18mfd: intel-lpss: Add Intel Emmitsburg PCH PCI IDsAndy Shevchenko1-0/+3
Intel Emmitsburg PCH has the same LPSS than Intel Ice Lake. Add the new IDs to the list of supported devices. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2020-05-26mfd: intel-lpss: Update LPSS UART #2 PCI ID for Jasper LakeAndy Shevchenko1-1/+1
It appears that preliminary documentation has a typo in the ID list, i.e. LPSS UART #2 had been advertised wrongly. Fix the driver according to the EDS v0.9. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2020-03-30mfd: intel-lpss: Fix Intel Elkhart Lake LPSS I2C input clockJarkko Nikula1-8/+13
Intel Elkhart Lake LPSS I2C has 100 MHz input clock instead of 133 MHz that was our preliminary information. This will result slower I2C bus clock when driver calculates its timing parameters in case ACPI tables don't provide them. Slower I2C bus clock is allowed but let's fix this to match with reality. While at it, keep the same default I2C device properties as Intel Broxton since it is not known do they need any update. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2020-03-30mfd: intel-lpss: Add Intel Comet Lake PCH-V PCI IDsAndy Shevchenko1-0/+10
Intel Comet Lake PCH-V has the same LPSS than Intel Kaby Lake. Add the new IDs to the list of supported devices. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2020-01-24mfd: intel-lpss: Add Intel Jasper Lake PCI IDsAndy Shevchenko1-0/+13
Intel Jasper Lake has the same LPSS than Intel Ice Lake. Add the new IDs to the list of supported devices. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-11-11mfd: intel-lpss: Add Intel Comet Lake PCH-H PCI IDsAndy Shevchenko1-1/+12
Intel Comet Lake PCH-H has the same LPSS than Intel Cannon Lake. Add the new IDs to the list of supported devices. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-11-11mfd: intel-lpss: Add default I2C device properties for Gemini LakeJarkko Nikula1-8/+20
It turned out Intel Gemini Lake doesn't use the same I2C timing parameters as Broxton. I got confirmation from the Windows team that Gemini Lake systems should use updated timing parameters that differ from those used in Broxton based systems. Fixes: f80e78aa11ad ("mfd: intel-lpss: Add Intel Gemini Lake PCI IDs") Tested-by: Chris Chiu <chiu@endlessm.com> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-08-12mfd: intel-lpss: Add Intel Tiger Lake PCI IDsAndy Shevchenko1-0/+23
Intel Tiger Lake has the same LPSS than Intel Broxton. Add the new IDs to the list of supported devices. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-08-12mfd: intel-lpss: Remove D3cold delayKai-Heng Feng1-0/+2
Goodix touchpad may drop its first couple input events when i2c-designware-platdrv and intel-lpss it connects to took too long to runtime resume from runtime suspended state. This issue happens becuase the touchpad has a rather small buffer to store up to 13 input events, so if the host doesn't read those events in time (i.e. runtime resume takes too long), events are dropped from the touchpad's buffer. The bottleneck is D3cold delay it waits when transitioning from D3cold to D0, hence remove the delay to make the resume faster. I've tested some systems with intel-lpss and haven't seen any regression. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=202683 Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-07-16Merge tag 'mfd-next-5.3' of ↵Linus Torvalds1-3/+18
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd Pull MFD updates from Lee Jones: "Core Frameworks: - Set 'struct device' fwnode when registering a new device New Drivers: - Add support for ROHM BD70528 PMIC New Device Support: - Add support for LP87561 4-Phase Regulator to TI LP87565 PMIC - Add support for RK809 and RK817 to Rockchip RK808 - Add support for Lid Angle to ChromeOS core - Add support for CS47L15 CODEC to Madera core - Add support for CS47L92 CODEC to Madera core - Add support for ChromeOS (legacy) Accelerometers in ChromeOS core - Add support for Add Intel Elkhart Lake PCH to Intel LPSS New Functionality: - Provide regulator supply information when registering; madera-core - Additional Device Tree support; lp87565, madera, cros-ec, rohm,bd71837-pmic - Allow over-riding power button press via Device Tree; rohm-bd718x7 - Differentiate between running processors; cros_ec_dev Fix-ups: - Big header file update; cros_ec_commands.h - Split header per-subsystem; rohm-bd718x7 - Remove superfluous code; menelaus, cs5535-mfd, cs47lXX-tables - Trivial; sorting, coding style; intel-lpss-pci - Only remove Power Off functionality if set locally; rk808 - Make use for Power Off Prepare(); rk808 - Fix spelling mistake in header guards; stmfx - Properly free IDA resources - SPDX fixups; cs47lXX-tables, madera - Error path fixups; hi655x-pmic Bug Fixes: - Add missing break in case() statement - Repair undefined behaviour when not initialising variables; arizona-core, madera-core - Fix reference to Device Tree documentation; madera" * tag 'mfd-next-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (45 commits) mfd: hi655x-pmic: Fix missing return value check for devm_regmap_init_mmio_clk mfd: madera: Fixup SPDX headers mfd: madera: Remove some unused registers and fix some defaults mfd: intel-lpss: Release IDA resources mfd: intel-lpss: Add Intel Elkhart Lake PCH PCI IDs mfd: cs5535-mfd: Remove ifdef OLPC noise mfd: stmfx: Fix macro definition spelling dt-bindings: mfd: Add link to ROHM BD71847 Datasheet MAINAINERS: Swap words in INTEL PMIC MULTIFUNCTION DEVICE DRIVERS mfd: cros_ec_dev: Register cros_ec_accel_legacy driver as a subdevice mfd: rk808: Prepare rk805 for poweroff mfd: rk808: Check pm_power_off pointer mfd: cros_ec: differentiate SCP from EC by feature bit dt-bindings: Add binding for cros-ec-rpmsg mfd: madera: Add Madera core support for CS47L92 mfd: madera: Add Madera core support for CS47L15 mfd: madera: Update DT bindings to add additional CODECs mfd: madera: Add supply mapping for MICVDD mfd: madera: Fix potential uninitialised use of variable mfd: madera: Fix bad reference to pinctrl.txt file ...
2019-07-02mfd: intel-lpss: Add Intel Elkhart Lake PCH PCI IDsAndy Shevchenko1-0/+15
Intel Elkhart Lake has the same LPSS than Intel Broxton. Add the new IDs to the list of supported devices. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-07-02mfd: intel-lpss: Keep device tables sorted by IDAndy Shevchenko1-3/+3
Easier to find and maintain if the device tables sorted by ID. Do it here for intel-lpss MFD driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner1-4/+1
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-14mfd: intel-lpss: Add Intel Comet Lake PCI IDsAndy Shevchenko1-0/+13
Intel Comet Lake has the same LPSS than Intel Cannon Lake. Add the new IDs to the list of supported devices. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Tested-by: Evan Green <evgreen@chromium.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-02-18mfd: intel-lpss: Move linux/pm.h to the local headerAndy Shevchenko1-1/+0
We now using a common macro for PM operations in Intel LPSS driver, and, since that macro relies on the definition and macro from linux/pm.h header file, it's logical to include it directly in intel-lpss.h. Otherwise it's a bit fragile and requires a proper ordering of header inclusion in C files. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2018-07-27mfd: intel-lpss: Add Ice Lake PCI IDsMika Westerberg1-0/+13
Intel Ice Lake has the same LPSS than Intel Cannon Lake. Add the new IDs to the list of supported devices. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2018-06-04mfd: intel-lpss: Fix Intel Cannon Lake LPSS I2C input clockJarkko Nikula1-10/+15
Intel Cannon Lake PCH has much higher 216 MHz input clock to LPSS I2C than Sunrisepoint which uses 120 MHz. Preliminary information was that both share the same clock rate but actual silicon implements elevated rate for better support for 3.4 MHz high-speed I2C. This incorrect input clock rate results too high I2C bus clock in case ACPI doesn't provide tuned I2C timing parameters since I2C host controller driver calculates them from input clock rate. Fix this by using the correct rate. We still share the same 230 ns SDA hold time value than Sunrisepoint. Cc: stable@vger.kernel.org Fixes: b418bbff36dd ("mfd: intel-lpss: Add Intel Cannonlake PCI IDs") Reported-by: Jian-Hong Pan <jian-hong@endlessm.com> Reported-by: Chris Chiu <chiu@endlessm.com> Reported-by: Daniel Drake <drake@endlessm.com> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Tested-by: Jian-Hong Pan <jian-hong@endlessm.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2017-09-05mfd: intel-lpss: Add missing PCI ID for Intel Sunrise Point LPSS devicesFlorian R. Hölzlwimmer1-0/+1
This patch adds a missing PCI ID of the Intel Sunrise Point chipset to the Intel LPSS driver. It fixes a bug causing the touchpad of the Lenovo Yoga 720-15 not to be recognized. See also bug 1700657 on bugs.launchpad.net. Many thanks to CoolStar, who found this solution! Reported-by: CoolStar <coolstarorganization@gmail.com> Tested-by: Mike Schwartz <mykesx@gmail.com> Tested-by: Björn Dahlgren <bjodah@gmail.com> Signed-off-by: Florian R. Hölzlwimmer <git.ich@frhoelzlwimmer.de> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2017-07-06mfd: intel-lpss: Add Intel Cannonlake PCI IDsAndy Shevchenko1-0/+24
Intel Cannonlake PCH has the same LPSS than Intel Kabylake. Add the new IDs to the list of supported devices. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2017-02-13mfd: intel-lpss: Add Intel Gemini Lake PCI IDsAndy Shevchenko1-1/+16
Intel Gemini Lake is essentially Broxton with different PCI IDs. Add these new PCI IDs to the list of supported devices. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-12-19Merge tag 'mfd-for-linus-4.10' of ↵Linus Torvalds1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd Pull MFD updates from Lee Jones: "New Device Support - Add support for Ricoh RC5T619 PMIC to rn5t618 - Add support for PM8821 PMIC to qcom-pm8xxx New Functionality: - Add support for GPIO to lpc_ich - Add support for GPADC to sun4i - Add ability for rk808 to shutdown Fix-ups: - Simplify/strip unnecessary code; tps65218, palmas, tps65217 - Device Tree binding updates; tps65218, altera-a10sr - Provide/export device ID info; tps65218, axp20x-i2c, hi655x-pmic, fsl-imx25-tsadc, intel_soc_pmic_bxtwc - Use MFD API instead of of_platform_populate(); tps65218 - Generalise name-space; pm8xxx - Supply/edit regmap configuration; axp20x, cs47l24-tables, axp20x - Enable compile testing; max77620, max77686, exynos-lpass, abx500-core - Coding style issues; wm8994-core, wm5102-tables - Supply endian support; syscon - Remove module support; ab3100-core, ab8500-debugfs, ab8500-gpadc, abx500-core Bug Fixes: - Fix ordering issues; wm8994 - Fix dependencies (build-time/run-time); exynos_lpass, sun4i-gpadc - Fix compiler warnings; sun4i-gpadc - Fix leaks; mfd-core - Fix page fault during module unload; tps65217" * tag 'mfd-for-linus-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (49 commits) mfd: tps65217: Support an interrupt pin as the system wakeup mfd: tps65217: Make an interrupt handler simpler mfd: tps65217: Update register interrupt mask bits instead of writing operation mfd: tps65217: Specify the IRQ name mfd: tps65217: Fix page fault on unloading modules mfd: palmas: Remove redundant check in palmas_power_off mfd: arizona: Disable IRQs during driver remove mfd: pm8xxx: add support to pm8821 mfd: intel-lpss: Try to enable Memory-Write-Invalidate mfd: rn5t618: Add Ricoh RC5T619 PMIC support mfd: axp20x: Add address extension registers for AXP806 regmap mfd: intel_soc_pmic_bxtwc: Fix a typo in MODULE_DEVICE_TABLE() mfd: core: Fix device reference leak in mfd_clone_cell mfd: bcm590xx: Simplify a test mfd: sun4i-gpadc: Select regmap-irq mfd: abx500-core: drop unused MODULE_ tags from non-modular code mfd: ab8500: make sysctrl explicitly non-modular mfd: ab8500-gpadc: Make it explicitly non-modular mfd: ab8500-debugfs: Make it explicitly non-modular mfd: ab8500-core: Make it explicitly non-modular ...
2016-11-29mfd: intel-lpss: Try to enable Memory-Write-InvalidateAndy Shevchenko1-0/+1
Enable MWI mechanism if PCI bus master supports it. It might be potential benefit in some cases. Documentation [1] says that standard Memory Write might supply more current data than in the CPU modified cache line and "trashing a line in the cache may trash some data that is more current that in the memory line". This allows to avoid potential retries and other performance degradation issues on the bus. [1] PCI System Architecture, 4th edition, ISBN: 0-201-30974-2, pp.117-119. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-11-16mfd: lpss: Fix Intel Kaby Lake PCH-H propertiesJarkko Nikula1-22/+9
There are a few issues on Intel Kaby Lake PCH-H properties added by commit a6a576b78e09 ("mfd: lpss: Add Intel Kaby Lake PCH-H PCI IDs"): - Input clock of I2C controller on Intel Kaby Lake PCH-H is 120 MHz not 133 MHz. This was probably copy-paste error from Intel Broxton I2C properties. - There is no default I2C SDA hold time specified which is used when ACPI doesn't provide it. I got information from Windows driver team that Kaby Lake PCH-H can use the same configuration than Intel Sunrisepoint PCH. - Common HS-UART properties are not used. Fix these by reusing the Sunrisepoint properties on Kaby Lake PCH-H. Fixes: a6a576b78e09 ("mfd: lpss: Add Intel Kaby Lake PCH-H PCI IDs") Reported-by: Xiang A Wang <xiang.a.wang@intel.com> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-05 01:28:42 +0300