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path: root/drivers/mfd/intel_soc_pmic_crc.c
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2017-09-05mfd: intel_soc_pmic: Export separate mfd-cell configs for BYT and CHTHans de Goede1-4/+23
Both Bay and Cherry Trail devices may be used together with a Crystal Cove PMIC. Each platform has its own variant of the PMIC, which both use the same ACPI HID, but they are not 100% compatible. Looking at the android x86 kernel sources where most of the Crystal Cove code comes from, it talks about "Valley View", "Bay Trail" and / or BYT without ever mentioning Cherry Trail, with the exception of the regulator driver. The Asus Zenfone-2 kernel code has 2 regulator drivers, one for Crystal Cove and one for what it calls Crystal Cove Plus. The Crystal Cove Plus regulator driver is the only one to mention Cherry Trail and that driver uses different register addresses then the normal (Bay Trail) Crystal Cove regulator driver, showing that at least the regulator register addresses are different. The GPIO code should work on both, and the PWM code is known to work on both and is necessary for backlight control on some Cherry Trail devices. Testing has shown that the ACPI OpRegion code otoh is causing problems on Cherry Trail devices, which is not surprising as it deals with the regulators and those have different register addresses on CHT. Specifically the ACPI OpRegion code causes the external microsd slot on a Dell Venue 8 5855 (Cherry Trail version) to not work and the eMMC to become unreliable and throw lots of errors. This commit replaces the single mfd_cell array currently used for Crystal Cove with 2 separate arrays, one for the Bay Trail variant and one for the Cherry Trail variant, note that the Cherry Trail version of the array only contains gpio and pwm cells. The PMIC OpRegion cell is deliberately not included and drivers for the other cells in the Bay Trail cell array were never upstreamed. Fixes: 7cf0a66f32 ("mfd: intel_soc_pmic: Crystal Cove support") Reported-and-tested-by: russianneuromancer <russianneuromancer@ya.ru> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2015-07-21mfd: intel_soc_pmic_crc: Add PWM cell device for Crystalcove PMICShobhit Kumar1-0/+3
Needed for PWM control suuported by the PMIC CC: Samuel Ortiz <sameo@linux.intel.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Thierry Reding <thierry.reding@gmail.com> Acked-by: Lee Jones <lee.jones@linaro.org> Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-06-22mfd: Constify regmap and irq configuration dataKrzysztof Kozlowski1-1/+1
Constify in various drivers configuration data which is not modified: - regmap_irq_chip, - individual regmap_irq's in array, - regmap_config, - irq_domain_ops, Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2015-01-22mfd: intel_soc_pmic: Constify struct regmap_configKrzysztof Kozlowski1-1/+1
The regmap_config struct may be const because it is not modified by the driver and regmap_init() accepts pointer to const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2014-11-27ACPI / PMIC: support PMIC operation region for CrystalCoveAaron Lu1-0/+3
The Baytrail-T platform firmware has defined two customized operation regions for PMIC chip Crystal Cove - one is for power resource handling and one is for thermal: sensor temperature reporting, trip point setting, etc. This patch adds support for them on top of the existing Crystal Cove PMIC driver. The reason to split code into a separate file intel_pmic.c is that there are more PMIC drivers with ACPI operation region support coming and we can re-use those code. The intel_pmic_opregion_data structure is created also for this purpose: when we need to support a new PMIC's operation region, we just need to fill those callbacks and the two register mapping tables. Signed-off-by: Aaron Lu <aaron.lu@intel.com> Acked-by: Lee Jones <lee.jones@linaro.org> for the MFD part Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2014-06-17mfd: intel_soc_pmic: Crystal Cove supportZhu, Lejun1-0/+158
This patch provides chip-specific support for Crystal Cove. Crystal Cove is the PMIC in Baytrail-T platform. Also adds Intel SoC PMIC support to the build files. Signed-off-by: Yang, Bin <bin.yang@intel.com> Signed-off-by: Zhu, Lejun <lejun.zhu@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>