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2023-05-04Merge tag 'ubifs-for-linus-6.4-rc1' of ↵Linus Torvalds2-6/+15
git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs Pull UBI and UBIFS updates from Richard Weinberger: "UBI: - Fix error value for try_write_vid_and_data() - Minor cleanups UBIFS: - Fixes for various memory leaks - Minor cleanups" * tag 'ubifs-for-linus-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs: ubifs: Fix memleak when insert_old_idx() failed Revert "ubifs: dirty_cow_znode: Fix memleak in error handling path" ubifs: Fix memory leak in do_rename ubifs: Free memory for tmpfile name ubi: Fix return value overwrite issue in try_write_vid_and_data() ubifs: Remove return in compr_exit() ubi: Simplify bool conversion
2023-04-27Merge tag 'driver-core-6.4-rc1' of ↵Linus Torvalds2-3/+1
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core updates from Greg KH: "Here is the large set of driver core changes for 6.4-rc1. Once again, a busy development cycle, with lots of changes happening in the driver core in the quest to be able to move "struct bus" and "struct class" into read-only memory, a task now complete with these changes. This will make the future rust interactions with the driver core more "provably correct" as well as providing more obvious lifetime rules for all busses and classes in the kernel. The changes required for this did touch many individual classes and busses as many callbacks were changed to take const * parameters instead. All of these changes have been submitted to the various subsystem maintainers, giving them plenty of time to review, and most of them actually did so. Other than those changes, included in here are a small set of other things: - kobject logging improvements - cacheinfo improvements and updates - obligatory fw_devlink updates and fixes - documentation updates - device property cleanups and const * changes - firwmare loader dependency fixes. All of these have been in linux-next for a while with no reported problems" * tag 'driver-core-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (120 commits) device property: make device_property functions take const device * driver core: update comments in device_rename() driver core: Don't require dynamic_debug for initcall_debug probe timing firmware_loader: rework crypto dependencies firmware_loader: Strip off \n from customized path zram: fix up permission for the hot_add sysfs file cacheinfo: Add use_arch[|_cache]_info field/function arch_topology: Remove early cacheinfo error message if -ENOENT cacheinfo: Check cache properties are present in DT cacheinfo: Check sib_leaf in cache_leaves_are_shared() cacheinfo: Allow early level detection when DT/ACPI info is missing/broken cacheinfo: Add arm64 early level initializer implementation cacheinfo: Add arch specific early level initializer tty: make tty_class a static const structure driver core: class: remove struct class_interface * from callbacks driver core: class: mark the struct class in struct class_interface constant driver core: class: make class_register() take a const * driver core: class: mark class_release() as taking a const * driver core: remove incorrect comment for device_create* MIPS: vpe-cmp: remove module owner pointer from struct class usage. ...
2023-04-27Merge tag 'spi-v6.4' of ↵Linus Torvalds1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "A fairly standard release for SPI with the exception of a change to the API for specifying chip selects done in preparation for supporting devices with more than one chip select, this required some mechanical changes throughout the tree which have been cooking in -next happily for a while. There's also a new API to allow us to support TPM chips on half duplex controllers. Summary: - Refactoring in preparation for supporting multiple chip selects for a single device, needed by some flash devices, which required a change in the SPI device API visible throughout the tree - Support for hardware assisted interaction with SPI TPMs on half duplex controllers, implemented on nVidia Tedra210 QuadSPI - Optimisation for large transfers on fsl-cpm devices - Cleanups around device property use which fix some sisues with fwnode - Use of both void remove() and devm_platform_.*ioremap_resource() - Support for AMD Pensando Elba, Amlogic A1, Cadence device mode, Intel MetorLake-S and StarFive J7110 QuadSPI" * tag 'spi-v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (185 commits) spi: bcm63xx: use macro DEFINE_SIMPLE_DEV_PM_OPS spi: tegra210-quad: Enable TPM wait polling spi: Add TPM HW flow flag spi: bcm63xx: remove PM_SLEEP based conditional compilation spi: cadence-quadspi: use macro DEFINE_SIMPLE_DEV_PM_OPS spi: spi-cadence: Add support for Slave mode spi: spi-cadence: Switch to spi_controller structure spi: cadence-quadspi: fix suspend-resume implementations spi: dw: Add support for AMD Pensando Elba SoC spi: dw: Add AMD Pensando Elba SoC SPI Controller spi: cadence-quadspi: Disable the SPI before reconfiguring spi: cadence-quadspi: Update the read timeout based on the length spi: spi-loopback-test: Add module param for iteration length spi: add support for Amlogic A1 SPI Flash Controller dt-bindings: spi: add Amlogic A1 SPI controller spi: fsl-spi: No need to check transfer length versus word size spi: fsl-spi: Change mspi_apply_cpu_mode_quirks() to void spi: fsl-cpm: Use 16 bit mode for large transfers with even size spi: fsl-spi: Re-organise transfer bits_per_word adaptation spi: fsl-spi: Fix CPM/QE mode Litte Endian ...
2023-04-26Merge tag 'mtd/for-6.4' of ↵Linus Torvalds77-398/+1359
git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull mtd updates from Miquel Raynal: "Core MTD changes: - dt-bindings: Drop unneeded quotes - mtdblock: Tolerate corrected bit-flips - Use of_property_read_bool() for boolean properties - Avoid magic values - Avoid printing error messages on probe deferrals - Prepare mtd_otp_nvmem_add() to handle -EPROBE_DEFER - Fix error path for nvmem provider - Fix nvmem error reporting - Provide unique name for nvmem device MTD device changes: - lpddr_cmds: Remove unused words variable - bcm63xxpart: Remove MODULE_LICENSE in non-modules SPI NOR core changes: - Introduce Read While Write support for flashes featuring several banks - Set the 4-Byte Address Mode method based on SFDP data - Allow post_sfdp hook to return errors - Parse SCCR MC table and introduce support for multi-chip devices SPI NOR manufacturer drivers changes: - macronix: Add support for mx25uw51245g with RWW - spansion: - Determine current address mode at runtime as it can be changed in a non-volatile way and differ from factory defaults or from what SFDP advertises. - Enable JFFS2 write buffer mode for few ECC'd NOR flashes: S25FS256T, s25hx and s28hx - Add support for s25hl02gt and s25hs02gt Raw NAND core changes: - Convert to platform remove callback returning void - Fix spelling mistake waifunc() -> waitfunc() Raw NAND controller driver changes: - imx: Remove unused is_imx51_nfc and imx53_nfc functions - omap2: Drop obsolete dependency on COMPILE_TEST - orion: Use devm_platform_ioremap_resource() - qcom: - Use of_property_present() for testing DT property presence - Use devm_platform_get_and_ioremap_resource() - stm32_fmc2: Depends on ARCH_STM32 instead of MACH_STM32MP157 - tmio: Remove reference to config MTD_NAND_TMIO in the parsers Raw NAND manufacturer driver changes: - hynix: Fix up bit 0 of sdr_timing_mode SPI-NAND changes: - Add support for ESMT F50x1G41LB" * tag 'mtd/for-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (55 commits) mtd: nand: Convert to platform remove callback returning void mtd: onenand: omap2: Drop obsolete dependency on COMPILE_TEST mtd: spi-nor: spansion: Add support for s25hl02gt and s25hs02gt mtd: spi-nor: spansion: Add a new ->ready() hook for multi-chip device mtd: spi-nor: spansion: Rework cypress_nor_quad_enable_volatile() for multi-chip device support mtd: spi-nor: spansion: Rework cypress_nor_get_page_size() for multi-chip device support mtd: spi-nor: sfdp: Add support for SCCR map for multi-chip device mtd: spi-nor: Extract volatile register offset from SCCR map mtd: spi-nor: Allow post_sfdp hook to return errors mtd: spi-nor: spansion: Rename method to cypress_nor_get_page_size mtd: spi-nor: spansion: Enable JFFS2 write buffer for S25FS256T mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s25hx SEMPER flash mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s28hx SEMPER flash mtd: spi-nor: spansion: Determine current address mode mtd: spi-nor: core: Introduce spi_nor_set_4byte_addr_mode() mtd: spi-nor: core: Update flash's current address mode when changing address mode mtd: spi-nor: Stop exporting spi_nor_restore() mtd: spi-nor: Set the 4-Byte Address Mode method based on SFDP data mtd: spi-nor: core: Make spi_nor_set_4byte_addr_mode_brwr public mtd: spi-nor: core: Update name and description of spi_nor_set_4byte_addr_mode ...
2023-04-21ubi: Fix return value overwrite issue in try_write_vid_and_data()Wang YanQing1-5/+14
The commit 2d78aee426d8 ("UBI: simplify LEB write and atomic LEB change code") adds helper function, try_write_vid_and_data(), to simplify the code, but this helper function has bug, it will return 0 (success) when ubi_io_write_vid_hdr() or the ubi_io_write_data() return error number (-EIO, etc), because the return value of ubi_wl_put_peb() will overwrite the original return value. This issue will cause unexpected data loss issue, because the caller of this function and UBIFS willn't know the data is lost. Fixes: 2d78aee426d8 ("UBI: simplify LEB write and atomic LEB change code") Cc: stable@vger.kernel.org Signed-off-by: Wang YanQing <udknight@gmail.com> Reviewed-by: Zhihao Cheng <chengzhihao1@huawei.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2023-04-21ubi: Simplify bool conversionYang Li1-1/+1
./drivers/mtd/ubi/build.c:1261:33-38: WARNING: conversion to bool not needed here Reported-by: Abaci Robot <abaci@linux.alibaba.com> Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=4061 Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Reviewed-by: Zhihao Cheng <chengzhihao1@huawei.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2023-04-19Merge tag 'nand/for-6.4' into mtd/nextMiquel Raynal56-211/+256
Raw NAND core changes: * Convert to platform remove callback returning void * Fix spelling mistake waifunc() -> waitfunc() Raw NAND controller driver changes: * imx: Remove unused is_imx51_nfc and imx53_nfc functions * omap2: Drop obsolete dependency on COMPILE_TEST * orion: Use devm_platform_ioremap_resource() * qcom: - Use of_property_present() for testing DT property presence - Use devm_platform_get_and_ioremap_resource() * stm32_fmc2: Depends on ARCH_STM32 instead of MACH_STM32MP157 * tmio: Remove reference to config MTD_NAND_TMIO in the parsers Raw NAND manufacturer driver changes: * hynix: Fix up bit 0 of sdr_timing_mode SPI-NAND changes: * Add support for ESMT F50x1G41LB Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2023-04-19Merge tag 'spi-nor/for-6.4' into mtd/nextMiquel Raynal15-158/+1074
SPI NOR core changes: * introduce Read While Write support for flashes featuring several banks * set the 4-Byte Address Mode method based on SFDP data * allow post_sfdp hook to return errors * parse SCCR MC table and introduce support for multi-chip devices SPI NOR manufacturer drivers changes: * macronix: add support for mx25uw51245g with RWW * spansion: - determine current address mode at runtime as it can be changed in a non-volatile way and differ from factory defaults or from what SFDP advertises. - enable JFFS2 write buffer mode for few ECC'd NOR flashes: S25FS256T, s25hx and s28hx - add support for s25hl02gt and s25hs02gt Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2023-04-16Merge tag 'ubifs-for-linus-6.3-rc7' of ↵Linus Torvalds2-8/+17
git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs Pull UBI fixes from Richard Weinberger: - Fix failure to attach when vid_hdr offset equals the (sub)page size - Fix for a deadlock in UBI's worker thread * tag 'ubifs-for-linus-6.3-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs: ubi: Fix failure attaching when vid_hdr offset equals to (sub)page size ubi: Fix deadlock caused by recursively holding work_sem
2023-04-11mtd: nand: Convert to platform remove callback returning voidUwe Kleine-König49-191/+99
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> # atmel Reviewed-by: Paul Cercueil <paul@crapouillou.net> # ingenic Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> # ingenic Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> # intel Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> # meson Acked-by: Roger Quadros <rogerq@kernel.org> # omap_elm Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas Reviewed-by: Heiko Stuebner <heiko@sntech.de> # rockchip Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> # sunxi Acked-by: Thierry Reding <treding@nvidia.com> # tegra Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230411113816.3472237-1-u.kleine-koenig@pengutronix.de
2023-04-11mtd: onenand: omap2: Drop obsolete dependency on COMPILE_TESTJean Delvare1-1/+1
Since commit 0166dc11be91 ("of: make CONFIG_OF user selectable"), it is possible to test-build any driver which depends on OF on any architecture by explicitly selecting OF. Therefore depending on COMPILE_TEST as an alternative is no longer needed. It is actually better to always build such drivers with OF enabled, so that the test builds are closer to how each driver will actually be built on its intended target. Building them without OF may not test much as the compiler will optimize out potentially large parts of the code. In the worst case, this could even pop false positive warnings. Dropping COMPILE_TEST here improves the quality of our testing and avoids wasting time on non-existent issues. Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Richard Weinberger <richard@nod.at> Cc: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230407190453.66efdf9d@endymion.delvare
2023-04-08mtd: spi-nor: spansion: Add support for s25hl02gt and s25hs02gtTakahiro Kuwano1-0/+12
Add ID, flags, and fixup for s25hl02gt and s25hs02gt. These parts are - Dual-die package parts - Not support chip erase - 4-byte addressing mode by default - Wrong param in SCCR map that needs to be fixed Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/55021d2409bf310692db0ac1c55e71ba406438a7.1680849425.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-08mtd: spi-nor: spansion: Add a new ->ready() hook for multi-chip deviceTakahiro Kuwano1-24/+85
For multi-chip devices, we need to make sure the all dice in the device are ready. The cypress_nor_sr_ready_and_clear() reads SR in each die and returns true only when all dice are ready. This function also takes care for program or erase error handling by reusing spansion_nor_clear_sr(). To do that, spansion_nor_clear_sr() is moved to top. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/3e4a64613ee733e002279349c75083433be45bf5.1680849425.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-08mtd: spi-nor: spansion: Rework cypress_nor_quad_enable_volatile() for ↵Takahiro Kuwano1-21/+39
multi-chip device support Rework quad method for multi-chip devices by updating CFR1V in all dice in the device. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/1b5606dbcc11b3432c306a75880f05c68e927fb9.1680849425.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-08mtd: spi-nor: spansion: Rework cypress_nor_get_page_size() for multi-chip ↵Takahiro Kuwano1-20/+69
device support For multi-chip devices, we can use 512B page only when the all dice are configured as 512B page size. The volatile register address is calculated by using the volatile register addresses retrieved from the SCCR tables and the (configuration) register offset. The location of cypress_nor_set_page_size() call is moved from post_bfpt_fixup() to post_sfdp_fixup(), because the number of dice and volatile register offset are parsed in the optional SCCR tables. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/6f8272f3e877dee392742d2c8401c4aed57e6d83.1680849425.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-08mtd: spi-nor: sfdp: Add support for SCCR map for multi-chip deviceTakahiro Kuwano1-0/+66
SCCR map for multi-chip devices contains the number of additional dice in the device and register offset values for each additional dice. spi_nor_parse_sccr_mc() is added to determine the number of dice and volatile register offset for each die. The volatile register offset table may already be allocated and contains offset value for die-0 via SCCR map parse. So, we should use devm_krealloc() to expand the table with preserving die-0 offset. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/89c892d52f8cbddbd14373f6a02db496885ae4f1.1680849425.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-08mtd: spi-nor: Extract volatile register offset from SCCR mapTakahiro Kuwano2-0/+17
In use of multi-chip devices, we need to access registers in each die for configuration and status check. The number of dice in the device and volatile register offsets for each die are essential to iterate register access ops. The volatile register offset for the first die resides in the 1st DWORD of SCCR map. Allocate the table and copy the offset value. The table may be allocated when the SCCR map for multi-chip is parsed. Since we cannot assume SCCR parse is always in ahead of SCCR multi-chip, we need to check if the table is already allocated or not. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/e2cc39ad6e0e02dd8288c4def9bb201a3f564425.1680849425.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-08mtd: spi-nor: Allow post_sfdp hook to return errorsTudor Ambarus4-10/+25
Multi die flashes like s25hl02gt need to determine the page_size at run-time by querying a configuration register for each die. Since the number of dice is determined in an optional SFDP table, SCCR MC, the page size configuration must be done in the post_sfdp hook. Allow post_sfdp to return errors, as reading the configuration register might return errors. Link: https://lore.kernel.org/r/924ab710f128448ec62537cfbb377336e390043c.1680849425.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-08mtd: spi-nor: spansion: Rename method to cypress_nor_get_page_sizeTudor Ambarus1-6/+5
The method queries SPINOR_REG_CYPRESS_CFR3V to determine the page size. Rename the method accordingly, s/set/get. Link: https://lore.kernel.org/r/cd3fb2cbc42a9576377ce4506eec72a58240805d.1680849425.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-08mtd: spi-nor: spansion: Enable JFFS2 write buffer for S25FS256TTakahiro Kuwano1-7/+1
Infineon(Cypress) SEMPER NOR flash family has on-die ECC and its program granularity is 16-byte ECC data unit size. JFFS2 supports write buffer mode for ECC'd NOR flash. Provide a way to clear the MTD_BIT_WRITEABLE flag in order to enable JFFS2 write buffer mode support. Drop the comment as the same info is now specified in cypress_nor_ecc_init(). Fixes: 6afcc84080c4 ("mtd: spi-nor: spansion: Add support for Infineon S25FS256T") Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/641bfb26c6e059915ae920117b7ec278df1a6f0a.1680760742.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-08mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s25hx SEMPER ↵Takahiro Kuwano1-5/+2
flash Infineon(Cypress) SEMPER NOR flash family has on-die ECC and its program granularity is 16-byte ECC data unit size. JFFS2 supports write buffer mode for ECC'd NOR flash. Provide a way to clear the MTD_BIT_WRITEABLE flag in order to enable JFFS2 write buffer mode support. Fixes: b6b23833fc42 ("mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups") Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/a1cc128e094db4ec141f85bd380127598dfef17e.1680760742.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-08mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s28hx SEMPER ↵Takahiro Kuwano4-1/+17
flash Infineon(Cypress) SEMPER NOR flash family has on-die ECC and its program granularity is 16-byte ECC data unit size. JFFS2 supports write buffer mode for ECC'd NOR flash. Provide a way to clear the MTD_BIT_WRITEABLE flag in order to enable JFFS2 write buffer mode support. A new SNOR_F_ECC flag is introduced to determine if the part has on-die ECC and if it has, MTD_BIT_WRITEABLE is unset. In vendor specific driver, a common cypress_nor_ecc_init() helper is added. This helper takes care for ECC related initialization for SEMPER flash family by setting up params->writesize and SNOR_F_ECC. Fixes: c3266af101f2 ("mtd: spi-nor: spansion: add support for Cypress Semper flash") Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/d586723f6f12aaff44fbcd7b51e674b47ed554ed.1680760742.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-04mtd: spi-nor: spansion: Determine current address modeTakahiro Kuwano1-3/+128
Internal address mode (3- or 4-byte) affects to the address length in Read Any Reg op. Read Any Reg op is used in SMPT parse and other setup functions. Current driver assumes that address mode is factory default but users can change it via volatile and non-volatile registers. Current address mode can be checked by CFR2V[7] but Read Any Reg op is needed to read CFR2V (chicken-and-egg). Introduce a way to determine current address mode by comparing status register 1 values read by different address length. Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/20230331074606.3559258-11-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-04mtd: spi-nor: core: Introduce spi_nor_set_4byte_addr_mode()Tudor Ambarus2-5/+31
Make the method public, as it will be used as a last resort to enable 4byte address mode when we can't determine the address mode at runtime. Update the addr_nbytes and current address mode while exiting the 4byte address mode too, as it may be used in the future by manufacturer drivers. No functional change. spi_nor_restore didn't update the address mode nbytes, but updating them now doesn't harm as the method is called in the driver's remove and shutdown paths. Link: https://lore.kernel.org/r/20230331074606.3559258-10-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-04mtd: spi-nor: core: Update flash's current address mode when changing ↵Tudor Ambarus1-1/+3
address mode The bug was obswerved while reading code. There are not many users of addr_mode_nbytes. Anyway, we should update the flash's current address mode when changing the address mode, fix it. We don't care for now about the set_4byte_addr_mode(nor, false) from spi_nor_restore(), as it is used at driver remove and shutdown. Fixes: d7931a215063 ("mtd: spi-nor: core: Track flash's internal address mode") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230331074606.3559258-9-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-04mtd: spi-nor: Stop exporting spi_nor_restore()Tudor Ambarus1-2/+1
Some SPI NOR controllers that used this method were moved to drivers/spi/. We don't accept new support for the existing SPI NOR controllers drivers under drivers/mtd/spi-nor/controllers/ and we encourage their owners to move the drivers under drivers/spi/. Make spi_nor_restore() private as we're going to use it just in core.c. Link: https://lore.kernel.org/r/20230331074606.3559258-8-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-04mtd: spi-nor: Set the 4-Byte Address Mode method based on SFDP dataTudor Ambarus6-12/+71
JESD216 SFDP defines in BFPT methods to enter and exit the 4-Byte Address Mode. The flash parameters and settings that are retrieved from SFDP have higher precedence than the static initialized ones, because they should be more accurate and less error prone than those initialized statically. Parse and favor the BFPT-parsed set_4byte_addr_mode methods. Some regressions may be introduced by this patch, because the params->set_4byte_addr_mode method that was set either in spi_nor_init_default_params() or later overwritten in default_init() hooks, are now be overwritten with a different value based on the BFPT data. If that's the case, the fix is to introduce a post_bfpt fixup hook where one should fix the wrong BFPT info. Link: https://lore.kernel.org/r/20230331074606.3559258-7-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-04mtd: spi-nor: core: Make spi_nor_set_4byte_addr_mode_brwr publicTudor Ambarus2-1/+2
This method can be retrieved at BFPT parsing time. The method is described in JESD216 BFPT[SFDP_DWORD(16)], BIT(28) and BIT(20). Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20230331074606.3559258-6-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-04mtd: spi-nor: core: Update name and description of spi_nor_set_4byte_addr_modeTudor Ambarus4-6/+8
Rename method to spi_nor_set_4byte_addr_mode_en4b_ex4b and extend its description. This method is described in JESD216 BFPT[SFDP_DWORD(16)], BIT(31) and BIT(23). Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20230331074606.3559258-5-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-04mtd: spi-nor: core: Update name and description of spansion_set_4byte_addr_modeTudor Ambarus1-4/+9
Rename method to spi_nor_set_4byte_addr_mode_brwr and extend its description. This method is described in JESD216 BFPT[SFDP_DWORD(16)], BIT(28) and BIT(20). Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20230331074606.3559258-4-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-04mtd: spi-nor: core: Update name and description of ↵Tudor Ambarus3-5/+7
micron_st_nor_set_4byte_addr_mode Rename method to spi_nor_set_4byte_addr_mode_wren_en4b_ex4b and extend its description. This method is described in JESD216 BFPT[SFDP_DWORD(16)], BIT(30) and BIT(22). Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20230331074606.3559258-3-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-04mtd: spi-nor: core: Move generic method to core - ↵Tudor Ambarus3-24/+25
micron_st_nor_set_4byte_addr_mode This method is described in JESD216 BFPT[SFDP_DWORD(16)], BIT(30) and BIT(22). Move the method to core. Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20230331074606.3559258-2-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-04mtd: spi-nor: macronix: Add support for mx25uw51245g with RWWMiquel Raynal1-0/+3
Describe this new part and provide the RWW flag for it. There is no public datasheet, but here are the sfdp tables plus base testing to show it works. $ cat /sys/bus/spi/devices/spi0.0/spi-nor/partname mx25uw51245g $ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id c2813a $ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer macronix $ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp 53464450080104fd00070114400000ff8701011c900000ff0a0001080001 00ff05000105200100ff84000102340100ff0000000000000000ffffffff ffffffffe5208affffffff1f00ff00ff00ff00ffeeffffffffff00ffffff 00ff0c2010d800ff00ff87790100821200e27704674630b030b0f4bdd55c 000000ff101000200000000000007ca14800000000008888000000000000 00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8 727103b80000000090a3188200c069960000000000000000727100987271 00b8727100990000000072710098727100f872710099727100f900000000 00000000011501d0727106d8000086500000060100000000020001030002 00000000060100000000000072060002000000eec0697272717100d8f7f6 000a00001445988043060f0021dcffff $ md5sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp 047a884cf44d9ffc2a94d3ab37b48c63 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp $ dd if=/dev/urandom of=./qspi_test bs=1M count=6 6+0 records in 6+0 records out $ mtd_debug write /dev/mtd1 0 6291456 qspi_test Copied 6291456 bytes from qspi_test to address 0x00000000 in flash $ mtd_debug erase /dev/mtd1 0 6291456 Erased 6291456 bytes from address 0x00000000 in flash $ mtd_debug read /dev/mtd1 0 6291456 qspi_read Copied 6291456 bytes from address 0x00000000 in flash to qspi_read $ hexdump qspi_read 0000000 ffff ffff ffff ffff ffff ffff ffff ffff * 0600000 $ mtd_debug write /dev/mtd1 0 6291456 qspi_test Copied 6291456 bytes from qspi_test to address 0x00000000 in flash $ mtd_debug read /dev/mtd1 0 6291456 qspi_read Copied 6291456 bytes from address 0x00000000 in flash to qspi_read $ sha1sum qspi_test qspi_read d24a9523db829a0df688f34b8dc76a1383b74024 qspi_test d24a9523db829a0df688f34b8dc76a1383b74024 qspi_read Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20230331194620.839899-2-miquel.raynal@bootlin.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-04mtd: spi-nor: Delay the initialization of bank_sizeMiquel Raynal1-1/+2
Bank size is derived from the chip's size, which in spi_nor_init_default_params() can still be zero if the flash size is not specified at flash declaration. Let the flash size be updated by parsing SFDP and do the initialization of the bank size in spi_nor_late_init_params(). Flashes that don't define the SFDP tables must specify the flash size at declaration. Fixes: 9d6c5d64f028 ("mtd: spi-nor: Introduce the concept of bank") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20230331194620.839899-1-miquel.raynal@bootlin.com [ta: drop superfluous initialization in spi_nor_init_default_params(), reword commit message, add Fixes tag.] Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-04mtd: spi-nor: Fix a trivial typoMiquel Raynal1-1/+1
Fix a trivial typo in one of the core's comments. Fixes: 620df2497415 ("mtd: spi-nor: Introduce spi_nor_get_flash_info()") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20230331194726.840208-1-miquel.raynal@bootlin.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-04-03mtd: spinand: add support for ESMT F50x1G41LBChuanhong Guo3-1/+138
This patch adds support for ESMT F50L1G41LB and F50D1G41LB. It seems that ESMT likes to use random JEDEC ID from other vendors. Their 1G chips uses 0xc8 from GigaDevice and 2G/4G chips uses 0x2c from Micron. For this reason, the ESMT entry is named esmt_c8 with explicit JEDEC ID in variable name. Datasheets: https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50L1G41LB(2M).pdf https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50D1G41LB(2M).pdf Signed-off-by: Chuanhong Guo <gch981213@gmail.com> Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Tested-by: Martin Kurbanov <mmkurbanov@sberdevices.ru> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230329114240.378722-1-mmkurbanov@sberdevices.ru
2023-04-03mtd: rawnand: meson: fix bitmask for length in command wordArseniy Krasnov1-3/+3
Valid mask is 0x3FFF, without this patch the following problems were found: 1) [ 0.938914] Could not find a valid ONFI parameter page, trying bit-wise majority to recover it [ 0.947384] ONFI parameter recovery failed, aborting 2) Read with disabled ECC mode was broken. Fixes: 8fae856c5350 ("mtd: rawnand: meson: add support for Amlogic NAND flash controller") Cc: <Stable@vger.kernel.org> Signed-off-by: Arseniy Krasnov <AVKrasnov@sberdevices.ru> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/3794ffbf-dfea-e96f-1f97-fe235b005e19@sberdevices.ru
2023-04-03mtdblock: tolerate corrected bit-flipsBang Li1-4/+8
mtd_read() may return -EUCLEAN in case of corrected bit-flips.This particular condition should not be treated like an error. Signed-off-by: Bang Li <libang.linuxer@gmail.com> Fixes: e47f68587b82 ("mtd: check for max_bitflips in mtd_read_oob()") Cc: <stable@vger.kernel.org> # v3.7 Acked-by: Richard Weinberger <richard@nod.at> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230328163012.4264-1-libang.linuxer@gmail.com
2023-04-03mtd: rawnand: stm32_fmc2: use timings.mode instead of checking tRC_minChristophe Kerello1-1/+1
Use timings.mode value instead of checking tRC_min timing for EDO mode support. Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Fixes: 2cd457f328c1 ("mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driver") Cc: stable@vger.kernel.org #v5.10+ Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230328155819.225521-3-christophe.kerello@foss.st.com
2023-04-03mtd: rawnand: stm32_fmc2: remove unsupported EDO modeChristophe Kerello1-0/+3
Remove the EDO mode support from as the FMC2 controller does not support the feature. Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Fixes: 2cd457f328c1 ("mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driver") Cc: stable@vger.kernel.org #v5.4+ Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230328155819.225521-2-christophe.kerello@foss.st.com
2023-04-03Merge 6.3-rc5 into driver-core-nextGreg Kroah-Hartman8-11/+54
We need the fixes in here for testing, as well as the driver core changes for documentation updates to build on. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-04-02Merge tag 'driver-core-6.3-rc5' of ↵Linus Torvalds3-4/+23
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core fixes from Greg KH: "Here are three small changes for 6.3-rc5 semi-related to driver core stuff: - documentation update where we move the security_bugs file to a more relevant location. - mdt/spi-nor debugfs memory leak fix that's been floating around for a long time and acked by the maintainer - cacheinfo bugfix for a regression in 6.3-rc1 All have been in linux-next with no reported problems" * tag 'driver-core-6.3-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: cacheinfo: Fix LLC is not exported through sysfs Documentation/security-bugs: move from admin-guide/ to process/ mtd: spi-nor: fix memory leak when using debugfs_lookup()
2023-03-30ubi: Fix failure attaching when vid_hdr offset equals to (sub)page sizeZhihao Cheng1-6/+15
Following process will make ubi attaching failed since commit 1b42b1a36fc946 ("ubi: ensure that VID header offset ... size"): ID="0xec,0xa1,0x00,0x15" # 128M 128KB 2KB modprobe nandsim id_bytes=$ID flash_eraseall /dev/mtd0 modprobe ubi mtd="0,2048" # set vid_hdr offset as 2048 (one page) (dmesg): ubi0 error: ubi_attach_mtd_dev [ubi]: VID header offset 2048 too large. UBI error: cannot attach mtd0 UBI error: cannot initialize UBI, error -22 Rework original solution, the key point is making sure 'vid_hdr_shift + UBI_VID_HDR_SIZE < ubi->vid_hdr_alsize', so we should check vid_hdr_shift rather not vid_hdr_offset. Then, ubi still support (sub)page aligined VID header offset. Fixes: 1b42b1a36fc946 ("ubi: ensure that VID header offset ... size") Signed-off-by: Zhihao Cheng <chengzhihao1@huawei.com> Tested-by: Nicolas Schichan <nschichan@freebox.fr> Tested-by: Miquel Raynal <miquel.raynal@bootlin.com> # v5.10, v4.19 Signed-off-by: Richard Weinberger <richard@nod.at>
2023-03-29mtd: spi-nor: Enhance locking to support reads while writesMiquel Raynal1-16/+321
On devices featuring several banks, the Read While Write (RWW) feature is here to improve the overall performance when performing parallel reads and writes at different locations (different banks). The following constraints have to be taken into account: 1#: A single operation can be performed in a given bank. 2#: Only a single program or erase operation can happen on the entire chip (common hardware limitation to limit costs) 3#: Reads must remain serialized even though reads crossing bank boundaries are allowed. 4#: The I/O bus is unique and thus is the most constrained resource, all spi-nor operations requiring access to the spi bus (through the spi controller) must be serialized until the bus exchanges are over. So we must ensure a single operation can be "sent" at a time. 5#: Any other operation that would not be either a read or a write or an erase is considered requiring access to the full chip and cannot be parallelized, we then need to ensure the full chip is in the idle state when this occurs. All these constraints can easily be managed with a proper locking model: 1#: Is enforced by a bitfield of the in-use banks, so that only a single operation can happen in a specific bank at any time. 2#: Is handled by the ongoing_pe boolean which is set before any write or erase, and is released only at the very end of the operation. This way, no other destructive operation on the chip can start during this time frame. 3#: An ongoing_rd boolean allows to track the ongoing reads, so that only one can be performed at a time. 4#: An ongoing_io boolean is introduced in order to capture and serialize bus accessed. This is the one being released "sooner" than before, because we only need to protect the chip against other SPI accesses during the I/O phase, which for the destructive operations is the beginning of the operation (when we send the command cycles and possibly the data), while the second part of the operation (the erase delay or the programmation delay) is when we can do something else in another bank. 5#: Is handled by the three booleans presented above, if any of them is set, the chip is not yet ready for the operation and must wait. All these internal variables are protected by the existing lock, so that changes in this structure are atomic. The serialization is handled with a wait queue. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20230328154105.448540-8-miquel.raynal@bootlin.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-03-29mtd: spi-nor: Add a RWW flagMiquel Raynal3-0/+7
Introduce a new (no SFDP) flag for the feature that we are about to support: Read While Write. This means, if the chip has several banks and supports RWW, once a page of data to write has been transferred into the chip's internal SRAM, another read operation happening on a different bank can be performed during the tPROG delay. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20230328154105.448540-7-miquel.raynal@bootlin.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-03-29mtd: spi-nor: Prepare the introduction of a new locking mechanismMiquel Raynal1-6/+53
This commit alone just introduces two new "prepare and lock" pairs of helpers which do the exact same thing as before. They will soon be improved in a followup commit which actually brings the logic, but I figured out it was more readable to do it this way. One new pair is suffixed _pe which stands for "program and erase" and hence is being called by spi_nor_write() and spi_nor_erase(). The other pair is suffixed _rd which stands for "read" and hence is being called by spi_nor_read(). One note however, these extra helpers will need to know the operation range, so they come with two new parameters to define it. Otherwise there is no functional change. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20230328154105.448540-6-miquel.raynal@bootlin.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-03-29mtd: spi-nor: Separate preparation and lockingMiquel Raynal1-4/+20
While this operation will remain a single function call in the end, let's extract the logic of the [un]prepare calls within their own static helper. We will soon add new flavors of the *_[un]prepare_and_[un]lock() helpers, having the preparation logic outside will save us from duplicating code over and over again. There is no functional change. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20230328154105.448540-5-miquel.raynal@bootlin.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-03-29mtd: spi-nor: Reorder the preparation vs. locking stepsMiquel Raynal5-21/+18
The ->prepare()/->unprepare() hooks are now legacy, we no longer accept new drivers supporting them. The only remaining controllers using them acquires a per-chip mutex, which should not interfere with the rest of the operation done in the core. As a result, we should be safe to reorganize these helpers to first perform the preparation, before acquiring the core locks. This is necessary in order to be able to improve the locking mechanism in the core (coming next). No side effects are expected. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20230328154105.448540-4-miquel.raynal@bootlin.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-03-29mtd: spi-nor: Add a macro to define more banksMiquel Raynal1-0/+4
Most of the chips on the market only feature a single bank. However, new chips may support more than a single bank, with the possibility to parallelize some operations. Let's introduce an INFOB() macro which also takes a n_bank parameter. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20230328154105.448540-3-miquel.raynal@bootlin.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2023-03-29mtd: spi-nor: Introduce the concept of bankMiquel Raynal3-5/+13
SPI NOR chips are made of pages, which gathered in small groups make (erase) sectors. Sectors, gathered together, make banks inside the chip. Until now, there was only one bank per device supported, but we are about to introduce support for new chips featuring several banks (up to 4 so far) where different operations may happen in parallel. Let's allow describing these additional bank parameters, and let's do this independently of any other value (like the number of sectors) with an absolute value. By default we consider that all chips have a single bank. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20230328154105.448540-2-miquel.raynal@bootlin.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-27 11:48:52 +0300