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path: root/drivers/net/ethernet/microchip/sparx5/sparx5_main.h
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2022-11-21net: microchip: sparx5: Add VCAP debugFS supportSteen Hegelund1-0/+3
Add a debugFS root folder for Sparx5 and add a vcap folder underneath with the VCAP instances and the ports Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-11-03net: microchip: sparx5: add support for offloading pcp tableDaniel Machon1-0/+11
Add new registers and functions to support offload of pcp app entries. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-10-24net: microchip: sparx5: Adding initial VCAP API supportSteen Hegelund1-0/+6
This provides the initial VCAP API framework and Sparx5 specific VCAP implementation. When the Sparx5 Switchdev driver is initialized it will also initialize its VCAP module, and this hooks up the concrete Sparx5 VCAP model to the VCAP API, so that the VCAP API knows what VCAP instances are available. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-10-04Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski1-1/+1
Merge in the left-over fixes before the net-next pull-request. Conflicts: drivers/net/ethernet/mediatek/mtk_ppe.c ae3ed15da588 ("net: ethernet: mtk_eth_soc: fix state in __mtk_foe_entry_clear") 9d8cb4c096ab ("net: ethernet: mtk_eth_soc: add foe_entry_size to mtk_eth_soc") https://lore.kernel.org/all/6cb6893b-4921-a068-4c30-1109795110bb@tessares.net/ kernel/bpf/helpers.c 8addbfc7b308 ("bpf: Gate dynptr API behind CAP_BPF") 5679ff2f138f ("bpf: Move bpf_loop and bpf_for_each_map_elem under CAP_BPF") 8a67f2de9b1d ("bpf: expose bpf_strtol and bpf_strtoul to all program types") https://lore.kernel.org/all/20221003201957.13149-1-daniel@iogearbox.net/ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-10-03net: sparx5: Fix return type of sparx5_port_xmit_implNathan Huckleberry1-1/+1
The ndo_start_xmit field in net_device_ops is expected to be of type netdev_tx_t (*ndo_start_xmit)(struct sk_buff *skb, struct net_device *dev). The mismatched return type breaks forward edge kCFI since the underlying function definition does not match the function hook definition. The return type of sparx5_port_xmit_impl should be changed from int to netdev_tx_t. Reported-by: Dan Carpenter <error27@gmail.com> Link: https://github.com/ClangBuiltLinux/linux/issues/1703 Cc: llvm@lists.linux.dev Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-09-08net: sparx5: fix function return type to match actual typeCasper Andersson1-2/+2
Function returns error integer, not bool. Does not have any impact on functionality. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Casper Andersson <casper.casan@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20220906065815.3856323-1-casper.casan@gmail.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-08-29net: sparx5: add support for mrouter portsCasper Andersson1-0/+2
All multicast should be forwarded to mrouter ports. Mrouter ports must therefore be part of all active multicast groups, and override flooding from being disabled. Signed-off-by: Casper Andersson <casper.casan@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-08-29net: sparx5: add list for mdb entries in driverCasper Andersson1-0/+13
Keep track of all mdb entries in software for easy access. Signed-off-by: Casper Andersson <casper.casan@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-03-26net: sparx5: Refactor mdb handling according to feedbackCasper Andersson1-1/+2
- Remove mact_lookup and use new mact_find instead. - Make pgid_read_mask function. - Set PGID arbiter to start searching at PGID_BASE + 8. This is according to feedback on previous patch. https://lore.kernel.org/netdev/20220322081823.wqbx7vud4q7qtjuq@wse-c0155/T/#t Signed-off-by: Casper Andersson <casper.casan@gmail.com> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-03-26net: sparx5: Remove unused GLAG handling in PGIDCasper Andersson1-4/+0
Removes PGID handling for GLAG since it is not used yet. According to feedback on previous patch. https://lore.kernel.org/netdev/20220322081823.wqbx7vud4q7qtjuq@wse-c0155/T/#t Signed-off-by: Casper Andersson <casper.casan@gmail.com> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-03-21net: sparx5: Add mdb handlersCasper Andersson1-0/+2
Adds mdb handlers. Uses the PGID arbiter to find a free entry in the PGID table for the multicast group port mask. Signed-off-by: Casper Andersson <casper.casan@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-03-21net: sparx5: Add arbiter for managing PGID tableCasper Andersson1-0/+21
The PGID (Port Group ID) table holds port masks for different purposes. The first 72 are reserved for port destination masks, flood masks, and CPU forwarding. The rest are shared between multicast, link aggregation, and virtualization profiles. The GLAG area is reserved to not be used by anything else, since it is a subset of the MCAST area. The arbiter keeps track of which entries are in use. You can ask for a free ID or give back one you are done using. Signed-off-by: Casper Andersson <casper.casan@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-03-16net: sparx5: Use Switchdev fdb events for managing fdb entriesCasper Andersson1-1/+2
Changes the handling of fdb entries to use Switchdev events, instead of the previous "sync_bridge" and "sync_port" which only run when adding or removing VLANs on the bridge. Signed-off-by: Casper Andersson <casper.casan@gmail.com> Link: https://lore.kernel.org/r/20220314160918.4rfrrfgmbsf2pxl3@wse-c0155 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-03-04net: sparx5: Add support for ptp interruptsHoratiu Vultur1-0/+2
When doing 2-step timestamping the HW will generate an interrupt when it managed to timestamp a frame. It is the SW responsibility to read it from the FIFO. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-03-04net: sparx5: Update extraction/injection for timestampingHoratiu Vultur1-0/+32
Update both the extraction and injection to do timestamping of the frames. The extraction is always doing the timestamping while for injection is doing the timestamping only if it is configured. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-03-04net: sparx5: Implement SIOCSHWTSTAMP and SIOCGHWTSTAMPHoratiu Vultur1-0/+9
Implement the ioctl callbacks SIOCSHWTSTAMP and SIOCGHWTSTAMP to allow to configure the ports to enable/disable timestamping for TX. The RX timestamping is always enabled. The HW is capable to run both 1-step timestamping and 2-step timestamping. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-03-04net: sparx5: Add support for ptp clocksHoratiu Vultur1-0/+21
The sparx5 has 3 PHC. Enable each of them, for now all the timestamping is happening on the first PHC. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-03-04net: sparx5: Move ifh from port to local variableHoratiu Vultur1-1/+1
Currently the ifh is not changed, it is fixed for each frame for each port that is sent out. Move this on the stack because this ifh needs to be change based on the frames that are send out. This is needed for PTP frames. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-02-28net: sparx5: Add #include to remove warningCasper Andersson1-0/+2
main.h uses NUM_TARGETS from main_regs.h, but the missing include never causes any errors because everywhere main.h is (currently) included, main_regs.h is included before. But since it is dependent on main_regs.h it should always be included. Signed-off-by: Casper Andersson <casper.casan@gmail.com> Reviewed-by: Joacim Zetterling <joacim.zetterling@westermo.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-08-20net: sparx5: switchdev: adding frame DMA functionalitySteen Hegelund1-0/+69
This add frame DMA functionality to the Sparx5 platform. Ethernet frames can be extracted or injected autonomously to or from the device’s DDR3/DDR3L memory and/or PCIe memory space. Linked list data structures in memory are used for injecting or extracting Ethernet frames. The FDMA generates interrupts when frame extraction or injection is done and when the linked lists need updating. The FDMA implements two extraction channels, one per switch core port towards the VCore CPU system and a total of six injection channels. Extraction channels are mapped one-to-one to the CPU ports, while injection channels can be individually assigned to any CPU port. - FDMA channel 0 through 5 corresponds to CPU port 0 injection direction FDMA_CH_CFG[channel].CH_INJ_PORT is set to 0. - FDMA channel 0 through 5 corresponds to CPU port 1 injection direction when FDMA_CH_CFG[channel].CH_INJ_PORT is set to 1. - FDMA channel 6 corresponds to CPU port 0 extraction direction. - FDMA channel 7 corresponds to CPU port 1 extraction direction. The FDMA implements a strict priority scheme among channels. Extraction channels are prioritized over injection channels and secondarily channels with higher channel number are prioritized over channels with lower number. On the other hand, ports are being served on an equal-bandwidth principle both on injection and extraction directions. The equal-bandwidth principle will not force an equal bandwidth. Instead, it ensures that the ports perform at their best considering the operating conditions. When more than one injection channel is enabled for injection on the same CPU port, priority determines which channel can inject data. Ownership is re-arbitrated on frame boundaries. The FDMA processes linked lists of DMA Control Block Structures (DCBs). The DCBs have the same basic structure for both injection and extraction. A DCB must be placed on a 64-bit word-aligned address in memory. Each DCB has a per-channel configurable amount of associated data blocks in memory, where the frame data is stored. The data blocks that are used by extraction channels must be placed on 64-bit word aligned addresses in memory, and their length must be a multiple of 128 bytes. A DCB carries the pointer to the next DCB of the linked list, the INFO word which holds information for the DCB, and a pair of status word and memory pointer for every data block that it is associated with. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-24net: sparx5: add ethtool configuration and statistics supportSteen Hegelund1-0/+14
This adds statistic counters for the network interfaces provided by the driver. It also adds CPU port counters (which are not exposed by ethtool). This also adds support for configuring the network interface parameters via ethtool: speed, duplex, aneg etc. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-24net: sparx5: add calendar bandwidth allocation supportSteen Hegelund1-0/+4
This configures the Sparx5 calendars according to the bandwidth requested in the Device Tree nodes. It also checks if the total requested bandwidth is within the specs of the detected Sparx5 models limits. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-24net: sparx5: add switching supportSteen Hegelund1-0/+11
This adds SwitchDev support by hardware offloading the software bridge. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-24net: sparx5: add vlan supportSteen Hegelund1-0/+14
This adds Sparx5 VLAN support. Sparx5 has more VLAN features than provided here, but these will be added in later series. For now we only add the basic L2 features. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-24net: sparx5: add mactable supportSteen Hegelund1-0/+26
This adds the Sparx5 MAC tables: listening for MAC table updates and updating on request. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-24net: sparx5: add hostmode with phylink supportSteen Hegelund1-0/+33
This patch adds netdevs and phylink support for the ports in the switch. It also adds register based injection and extraction for these ports. Frame DMA support for injection and extraction will be added in a later series. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-24net: sparx5: add the basic sparx5 driverSteen Hegelund1-0/+273
This adds the Sparx5 basic SwitchDev driver framework with IO range mapping, switch device detection and core clock configuration. Support for ports, phylink, netdev, mactable etc. are in the following patches. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: David S. Miller <davem@davemloft.net>
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