summaryrefslogtreecommitdiff
path: root/drivers/pci/controller/dwc/pci-layerscape-ep.c
AgeCommit message (Collapse)AuthorFilesLines
2024-02-16PCI: endpoint: Clean up hardware description for BARsNiklas Cassel1-1/+4
The hardware description for BARs is scattered in many different variables in pci_epc_features. Some of these things are mutually exclusive, so it can create confusion over which variable that has precedence over another. Improve the situation by creating a struct pci_epc_bar_desc, and a new enum pci_epc_bar_type, and convert the endpoint controller drivers to use this more well defined format. Additionally, some endpoint controller drivers mark the BAR succeeding a "64-bit only BAR" as reserved, while some do not. By definition, a 64-bit BAR uses the succeeding BAR for the upper 32-bits, so an EPF driver cannot use a BAR succeeding a 64-bit BAR. Ensure that all endpoint controller drivers are uniform, and actually describe a reserved BAR as reserved. Signed-off-by: Niklas Cassel <cassel@kernel.org> Reviewed-by: Kishon Vijay Abraham I <kishon@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240216134524.1142149-2-cassel@kernel.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-01-15Merge branch 'pci/irq-clean-up'Bjorn Helgaas1-5/+5
- Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX to be more explicit and match spec terminology (Bjorn Helgaas) - Use existing PCI_IRQ_INTX, PCI_IRQ_MSI, PCI_IRQ_MSIX in artpec6, cadence, designware, designware-plat, dra7xx, imx6, keembay, keystone, layerscape, mhi, ntb, qcom, rcar, rcar-gen4, rockchip, tegra194, uniphier, vntb; drop the redundant pci_epc_irq_type enum with the same values (Damien Le Moal) - Use "intx" instead of "leg" or "legacy" when describing INTx interrupts in endpoint core, endpoint tests, cadence, dra7xx, designware, dw-rockchip, dwc core, imx6, keystone, layerscape, qcom, rcar-gen4, rockchip, tegra194, uniphier, xilinx-nwl (Damien Le Moal) * pci/irq-clean-up: PCI: xilinx-nwl: Use INTX instead of legacy PCI: rockchip-host: Rename rockchip_pcie_legacy_int_handler() PCI: rockchip-ep: Use INTX instead of legacy PCI: uniphier: Use INTX instead of legacy PCI: tegra194: Use INTX instead of legacy PCI: dw-rockchip: Rename rockchip_pcie_legacy_int_handler() PCI: keystone: Use INTX instead of legacy PCI: dwc: Rename dw_pcie_ep_raise_legacy_irq() PCI: cadence: Use INTX instead of legacy PCI: dra7xx: Rename dra7xx_pcie_raise_legacy_irq() misc: pci_endpoint_test: Use INTX instead of LEGACY PCI: endpoint: Rename LEGACY to INTX in test function driver PCI: endpoint: Use INTX instead of legacy PCI: endpoint: Drop PCI_EPC_IRQ_XXX definitions PCI: Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX
2024-01-15Merge branch 'pci/controller/layerscape'Bjorn Helgaas1-8/+8
- Add suspend/resume support for Layerscape LS1043a, including software-managed PME_Turn_Off and transitions between L0, L2/L3_Ready Link states (Frank Li) * pci/controller/layerscape: PCI: layerscape: Add suspend/resume for ls1043a PCI: layerscape(ep): Rename pf_* as pf_lut_* PCI: layerscape: Add suspend/resume for ls1021a PCI: layerscape: Add function pointer for exit_from_l2()
2024-01-06PCI: dwc: Rename .func_conf_select to .get_dbi_offset in struct dw_pcie_ep_opsYoshihiro Shimoda1-3/+2
Since the struct member .func_conf_select makes the intentions behind it difficult to ascertain from its name alone, rename it to .get_dbi_offset to make the intended usage more obvious. [kwilczynski: commmit log] Suggested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/linux-pci/20231220053829.1921187-4-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
2024-01-06PCI: dwc: Rename .ep_init to .init in struct dw_pcie_ep_opsYoshihiro Shimoda1-1/+1
Since the name of the dw_pcie_ep_ops struct makes it obvious that it's for the PCIe Endpoint, rename the struct member .ep_init to .init. [kwilczynski: commit log] Suggested-by: Serge Semin <fancer.lancer@gmail.com> Suggested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/linux-pci/20231220053829.1921187-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Reviewed-by: Srikanth Thokala <srikanth.thokala@intel.com> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2023-12-19PCI: dwc: Rename dw_pcie_ep_raise_legacy_irq()Damien Le Moal1-1/+1
Rename the function dw_pcie_ep_raise_legacy_irq() of the Designware endpoint controller driver to dw_pcie_ep_raise_intx_irq() to match the name of the PCI_IRQ_INTX macro. Link: https://lore.kernel.org/r/20231122060406.14695-10-dlemoal@kernel.org Signed-off-by: Damien Le Moal <dlemoal@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
2023-12-18PCI: endpoint: Drop PCI_EPC_IRQ_XXX definitionsDamien Le Moal1-4/+4
linux/pci.h defines the IRQ flags PCI_IRQ_INTX, PCI_IRQ_MSI and PCI_IRQ_MSIX. Let's use these flags directly instead of the endpoint definitions provided by enum pci_epc_irq_type. This removes the need for defining this enum type completely. Link: https://lore.kernel.org/r/20231122060406.14695-3-dlemoal@kernel.org Signed-off-by: Damien Le Moal <dlemoal@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2023-12-12PCI: layerscape(ep): Rename pf_* as pf_lut_*Frank Li1-8/+8
'pf' and 'lut' are two different acronyms describing the same thing, basically it is a MMIO base address plus an offset. Rename them to avoid duplicate pf_* and lut_* naming schemes in the driver. Link: https://lore.kernel.org/r/20231204160829.2498703-4-Frank.Li@nxp.com Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Roy Zang <Roy.Zang@nxp.com>
2023-10-10PCI: layerscape-ep: Set 64-bit DMA maskGuanhua Gao1-0/+2
Set DMA mask and coherent DMA mask to enable 64-bit addressing. Link: https://lore.kernel.org/r/20230926140445.3855365-1-Frank.Li@nxp.com Signed-off-by: Guanhua Gao <guanhua.gao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Christoph Hellwig <hch@lst.de> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Roy Zang <Roy.Zang@nxp.com>
2023-08-24PCI: layerscape: Add workaround for lost link capabilities during resetXiaowei Bao1-0/+19
The endpoint controller loses the Maximum Link Width and Supported Link Speed value from the Link Capabilities Register - initially configured by the Reset Configuration Word (RCW) - during a link-down or hot reset event. Address this issue in the endpoint event handler. Link: https://lore.kernel.org/r/20230720135834.1977616-2-Frank.Li@nxp.com Fixes: a805770d8a22 ("PCI: layerscape: Add EP mode support") Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Acked-by: Manivannan Sadhasivam <mani@kernel.org>
2023-08-24PCI: layerscape: Add support for link-down notificationFrank Li1-0/+1
Add support to pass link-down notification to the endpoint function driver so that it can process the LINK_DOWN event. Link: https://lore.kernel.org/r/20230720135834.1977616-1-Frank.Li@nxp.com Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Acked-by: Manivannan Sadhasivam <mani@kernel.org>
2023-06-23PCI: layerscape: Add the endpoint linkup notifier supportFrank Li1-1/+99
Layerscape has PME interrupt, which can be used as linkup notifier. Set CFG_READY bit of PEX_PF0_CONFIG to enable accesses from root complex when linkup detected. Link: https://lore.kernel.org/r/20230515151049.2797105-1-Frank.Li@nxp.com Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2023-03-17PCI: layerscape: Add EP mode support for ls1028aXiaowei Bao1-0/+1
Add PCIe EP mode support for ls1028a. Link: https://lore.kernel.org/r/20230209151050.233973-1-Frank.Li@nxp.com Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Alok Tiwari <alok.a.tiwari@oracle.com> Acked-by: Roy Zang <Roy.Zang@nxp.com>
2022-07-06PCI: dwc: Add start_link/stop_link inlinesSerge Semin1-12/+0
Factor out this pattern: if (!pci->ops || !pci->ops->start_link) return -EINVAL; return pci->ops->start_link(pci); into a new dw_pcie_start_link() wrapper and do the same for the stop_link() method. Note that dw_pcie_ep_start() previously returned -EINVAL if there was no platform start_link() method, which didn't make much sense since that is not an error. It will now return 0 in that case. As a side-effect, drop the empty start_link() and dummy dw_pcie_ops instances from the generic DW PCIe and Layerscape EP platform drivers. [bhelgaas: commit log] Link: https://lore.kernel.org/r/20220624143428.8334-14-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2021-03-22PCI: layerscape: Correct syntax by changing comma to semicolonKrzysztof Wilczyński1-1/+1
Replace command with a semicolon to correct syntax and to prevent potential unspecified behaviour and/or unintended side effects. Related: https://lore.kernel.org/linux-pci/20201216131944.14990-1-zhengyongjun3@huawei.com/ Co-authored-by: Zheng Yongjun <zhengyongjun3@huawei.com> Link: https://lore.kernel.org/r/20210311033745.1547044-1-kw@linux.com Signed-off-by: Krzysztof Wilczyński <kw@linux.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Roy Zang <roy.zang@nxp.com>
2021-02-24PCI: layerscape: Add LX2160A rev2 EP mode supportHou Zhiqiang1-0/+7
The LX2160A rev2 uses the same PCIe IP as LS2088A, but LX2160A rev2 PCIe controller is integrated with different stride between PFs' register address. Link: https://lore.kernel.org/r/20201026051448.1913-2-Zhiqiang.Hou@nxp.com Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-11-19PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common codeRob Herring1-35/+2
Most DWC drivers use the common register resource names "dbi", "dbi2", and "addr_space", so let's move their setup into the DWC common code. This means 'dbi_base' in particular is setup later, but it looks like no drivers touch DBI registers before dw_pcie_host_init or dw_pcie_ep_init. Link: https://lore.kernel.org/r/20201105211159.1814485-4-robh@kernel.org Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Minghuan Lian <minghuan.Lian@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Roy Zang <roy.zang@nxp.com> Cc: Jonathan Chocron <jonnyc@amazon.com> Cc: Jesper Nilsson <jesper.nilsson@axis.com> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Cc: Xiaowei Song <songxiaowei@hisilicon.com> Cc: Binghui Wang <wangbinghui@hisilicon.com> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Stanimir Varbanov <svarbanov@mm-sol.com> Cc: Pratyush Anand <pratyush.anand@gmail.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: linux-omap@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-arm-kernel@axis.com Cc: linux-arm-msm@vger.kernel.org Cc: linux-tegra@vger.kernel.org
2020-09-21PCI: layerscape: Add EP mode support for ls1088a and ls2088aXiaowei Bao1-19/+53
Add PCIe EP mode support for ls1088a and ls2088a, there are some difference between LS1 and LS2 platform, so refactor the code of the EP driver. Link: https://lore.kernel.org/r/20200918080024.13639-10-Zhiqiang.Hou@nxp.com Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-09-21PCI: layerscape: Modify the MSIX to the doorbell modeXiaowei Bao1-1/+2
dw_pcie_ep_raise_msix_irq was never called in the exisitng driver before, because the ls1046a platform don't support the MSIX feature and msix_capable was always set to false. Now that add the ls1088a platform with MSIX support, use the doorbell method to support the MSIX feature. Link: https://lore.kernel.org/r/20200918080024.13639-9-Zhiqiang.Hou@nxp.com Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
2020-09-21PCI: layerscape: Modify the way of getting capability with different PEXXiaowei Bao1-8/+23
The different PCIe controller in one board may be have different capability of MSI or MSIX, so change the way of getting the MSI capability, make it more flexible. Link: https://lore.kernel.org/r/20200918080024.13639-8-Zhiqiang.Hou@nxp.com Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-09-21PCI: layerscape: Fix some format issue of the codeXiaowei Bao1-2/+2
Fix some format issue of the code in EP driver. Link: https://lore.kernel.org/r/20200918080024.13639-7-Zhiqiang.Hou@nxp.com Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
2019-10-14PCI: Add PCI_STD_NUM_BARS for the number of standard BARsDenis Efremov1-1/+1
Code that iterates over all standard PCI BARs typically uses PCI_STD_RESOURCE_END. However, that requires the unusual test "i <= PCI_STD_RESOURCE_END" rather than something the typical "i < PCI_STD_NUM_BARS". Add a definition for PCI_STD_NUM_BARS and change loops to use the more idiomatic C style to help avoid fencepost errors. Link: https://lore.kernel.org/r/20190927234026.23342-1-efremov@linux.com Link: https://lore.kernel.org/r/20190927234308.23935-1-efremov@linux.com Link: https://lore.kernel.org/r/20190916204158.6889-3-efremov@linux.com Signed-off-by: Denis Efremov <efremov@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Sebastian Ott <sebott@linux.ibm.com> # arch/s390/ Acked-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> # video/fbdev/ Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> # pci/controller/dwc/ Acked-by: Jack Wang <jinpu.wang@cloud.ionos.com> # scsi/pm8001/ Acked-by: Martin K. Petersen <martin.petersen@oracle.com> # scsi/pm8001/ Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # memstick/
2019-08-14PCI: layerscape: Add the bar_fixed_64bit property to the endpoint driverXiaowei Bao1-0/+1
The layerscape PCIe controller have 4 BARs. BAR0 and BAR1 are 32bit, BAR2 and BAR4 are 64bit and that's a fixed hardware configuration. Set the bar_fixed_64bit variable accordingly. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> [lorenzo.pieralisi@arm.com: commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-15PCI: dwc: Add const qualifier to struct dw_pcie_ep_opsKishon Vijay Abraham I1-1/+1
Add const qualifier to struct dw_pcie_ep_ops member of struct dw_pcie_ep. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2019-02-21PCI: layerscape: Add EP mode supportXiaowei Bao1-0/+156
Add the PCIe EP mode support to the layerscape platform controller. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Minghuan Lian <minghuan.lian@nxp.com> Reviewed-by: Zhiqiang Hou <zhiqiang.hou@nxp.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-10 06:17:35 +0300